[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for AMO instrs whose return values are unused

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw created this revision.
dtcxzyw added reviewers: craig.topper, asb, jrtc27, kito-cheng.
Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
dtcxzyw requested review of this revision.
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay.
Herald added a project: LLVM.

When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVOptAMOInstrs`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158759

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVOptAMOInstrs.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D158759.553185.patch
Type: text/x-patch
Size: 21821 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230824/68d11ce8/attachment.bin>