[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for AMO instrs whose return values are unused
Yingwei Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 10:50:09 PDT 2023
dtcxzyw created this revision.
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When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVOptAMOInstrs`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D158759
Files:
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVOptAMOInstrs.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
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