[PATCH] D158742: [RISCV] Detect bitcasted splat patterns

[Luke Lau via Phabricator via llvm-commits]

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A common issue in RV32 is that i64 splats of fixed length vectors are legalized
to (bitcast v2i64 (build_vector <i32 x, i32 y, i32 x, i32 y>)).

These are then lowered in RISCVISelLowering to something like:

(insert_subvector (bitcast (extract_subvector (vmv_v_x_vl))))

RV64 doesn't have this problem since the insert_subvector and extract_subvector pairs are usually combined away, but the bitcast introduced with SEW=64 on RV32 prevents this from happening.

This patch handles the case by peeking through the inserts, bitcasts and
extracts to detect the "hidden" splats.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158742

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

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