[llvm] 243d8cd - [RISCV] Add missed HasRoundModeOp for VPseudoUnaryMask_FRM/VPseudoUnaryMask_FRM.

[Yeting Kuo via llvm-commits]

Author: Yeting Kuo
Date: 2023-08-24T21:45:22+08:00
New Revision: 243d8cdb03142f0d142482f7a44931cc1a0138da

URL: https://github.com/llvm/llvm-project/commit/243d8cdb03142f0d142482f7a44931cc1a0138da
DIFF: https://github.com/llvm/llvm-project/commit/243d8cdb03142f0d142482f7a44931cc1a0138da.diff

LOG: [RISCV] Add missed HasRoundModeOp for VPseudoUnaryMask_FRM/VPseudoUnaryMask_FRM.

Missed HasRoundModeOp makes performCombineVMergeAndVOps use wrong operands for
VFCVT_RM instructions.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D158711

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 288b0890f3ee48..45755848204d0a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1102,6 +1102,7 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasVecPolicyOp = 1;
+  let HasRoundModeOp = 1;
   let usesCustomInserter = 1;
 }
 
@@ -1120,6 +1121,7 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
   let HasSEWOp = 1;
   let HasVecPolicyOp = 1;
   let UsesMaskPolicy = 1;
+  let HasRoundModeOp = 1;
   let usesCustomInserter = 1;
 }
 

diff  --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
index aef7ffbf5a8930..7e137d6a619692 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
@@ -240,3 +240,21 @@ define <vscale x 2 x i32> @vmerge_larger_vl_poison_passthru(<vscale x 2 x i32> %
   %b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %mask, i64 3)
   ret <vscale x 2 x i32> %b
 }
+
+; Test VFCVT_RM
+declare <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float>)
+declare <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1>, <vscale x 2 x i32>, <vscale x 2 x i32>, i32)
+define <vscale x 2 x i32> @vmerge_vfcvt_rm(<vscale x 2 x i32> %passthru, <vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vmerge_vfcvt_rm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fsrmi a1, 2
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    vfcvt.x.f.v v8, v9, v0.t
+; CHECK-NEXT:    fsrm a1
+; CHECK-NEXT:    ret
+entry:
+  %floor = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %a)
+  %i = fptosi <vscale x 2 x float> %floor to <vscale x 2 x i32>
+  %res = call <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1> %m, <vscale x 2 x i32> %i, <vscale x 2 x i32> %passthru, i32 %evl)
+  ret <vscale x 2 x i32> %res
+}