[llvm] f84cd7e - [X86] fold-and-shift-x86_64.ll - add zext test case where upper bits are known zero (and won't get simplified to any_extend)

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-24T11:47:07+01:00
New Revision: f84cd7e57913aa4462cf91d42ace4e5231735ac9

URL: https://github.com/llvm/llvm-project/commit/f84cd7e57913aa4462cf91d42ace4e5231735ac9
DIFF: https://github.com/llvm/llvm-project/commit/f84cd7e57913aa4462cf91d42ace4e5231735ac9.diff

LOG: [X86] fold-and-shift-x86_64.ll - add zext test case where upper bits are known zero (and won't get simplified to any_extend)

Add test coverage showing failure to use foldMaskAndShiftToScale with zero_extend nodes

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll b/llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
index 62abc4e035f4ac..964221d2434969 100644
--- a/llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
+++ b/llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
@@ -92,3 +92,20 @@ entry:
   ret i8 %tmp9
 }
 
+define i32 @t7(<16 x i8> %a0, ptr %p0) {
+; CHECK-LABEL: t7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pmovmskb %xmm0, %eax
+; CHECK-NEXT:    shrl %eax
+; CHECK-NEXT:    andl $-4, %eax
+; CHECK-NEXT:    movzbl (%rdi,%rax), %eax
+; CHECK-NEXT:    retq
+  %i = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0)
+  %index = lshr i32 %i, 1
+  %mask = and i32 %index, 16777212
+  %val.ptr = getelementptr inbounds i8, ptr %p0, i32 %mask
+  %val = load i8, ptr %val.ptr
+  %ext = zext i8 %val to i32
+  ret i32 %ext
+}
+declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>)