[PATCH] D158256: [RISCV] Fix assertion failure when zcmp extension is enabled.

[garvit gupta via Phabricator via llvm-commits]

garvitgupta08 added a comment.

In D158256#4605968 <https://reviews.llvm.org/D158256#4605968>, @garvitgupta08 wrote:

> When enabling zcmp extension to build compiler-rt, fixunstfsi.c was crashing at the above mentioned pass. The testcase used is reduced through bugpoint from the generated llvm IR from fixunstfsi.c source.

@jrtc27 I commented about the source of the IR used in MIR testcase. I didn't hear back on it so I thought the test currently is fine. Let me know if I should put the original IR in the testcase without reducing it through bugpoint so that it can more meaningful and readable.



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Comment at: llvm/test/CodeGen/RISCV/prolog-epilog-crash.mir:7
+--- |
+  define hidden void @f(fp128 %a) local_unnamed_addr #0 {
+  entry:
----------------
jrtc27 wrote:
> jrtc27 wrote:
> > garvitgupta08 wrote:
> > > garvitgupta08 wrote:
> > > > jrtc27 wrote:
> > > > > Is the IR actually needed?
> > > > Yes, I think that is how it has been done what other mir unit test cases. Besides it would help to see the .ll file from which the mir testcase is generated.
> > > There is a typo - //for// other mir unit testcases.
> > Not all MIR tests need it. So I'm asking whether this one specifically does.
> You've still not answered this
The only reason for me to include IR in the testcase is to know the source from which the Machine instructions are generated. If it does not help much in this case, I can remove it.


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https://reviews.llvm.org/D158256