[PATCH] D158623: [RISCV] Reorder the stack frame objects.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:528
+         Opcode == RISCV::LD || Opcode == RISCV::FLD || Opcode == RISCV::SW ||
+         (!STI.is64Bit() && Opcode == RISCV::FSW) || Opcode == RISCV::SD ||
+         Opcode == RISCV::FSD;
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Don't we need to check C or Zcf/Zcd for compressing FP loads and stores? They aren't compressible with just Zca.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:532
+
+void RISCVFrameLowering::orderFrameObjects(
+    const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
----------------
Just to confirm, the vector passed to this function does not include the emergency spill slot scavenging slots which must be kept to close to sp/fp?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158623/new/

https://reviews.llvm.org/D158623