[llvm] 1f39511 - [RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-08-23T16:57:16-07:00
New Revision: 1f395115da076bd2b5a5ccd2b18ee92ee85d146e

URL: https://github.com/llvm/llvm-project/commit/1f395115da076bd2b5a5ccd2b18ee92ee85d146e
DIFF: https://github.com/llvm/llvm-project/commit/1f395115da076bd2b5a5ccd2b18ee92ee85d146e.diff

LOG: [RISCV] Add Zicond instructions to RISCVOptWInstrs like XVentanaCondOps.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    llvm/test/CodeGen/RISCV/condops.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 0f6aba20d6cd45..bd294c669735f4 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -284,6 +284,8 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
         Worklist.push_back(std::make_pair(UserMI, Bits));
         break;
 
+      case RISCV::CZERO_EQZ:
+      case RISCV::CZERO_NEZ:
       case RISCV::VT_MASKC:
       case RISCV::VT_MASKCN:
         if (OpIdx != 1)
@@ -505,6 +507,8 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
       break;
     }
 
+    case RISCV::CZERO_EQZ:
+    case RISCV::CZERO_NEZ:
     case RISCV::VT_MASKC:
     case RISCV::VT_MASKCN:
       // Instructions return zero or operand 1. Result is sign extended if

diff  --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index 0c6e20f942c8d8..c405b0ae171784 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -3114,7 +3114,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
 ; RV64ZICOND-NEXT:    czero.eqz s1, a1, a0
 ; RV64ZICOND-NEXT:  .LBB54_1: # %bb2
 ; RV64ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64ZICOND-NEXT:    sext.w a0, s1
+; RV64ZICOND-NEXT:    mv a0, s1
 ; RV64ZICOND-NEXT:    call bar at plt
 ; RV64ZICOND-NEXT:    sllw s1, s1, s0
 ; RV64ZICOND-NEXT:    bnez a0, .LBB54_1
@@ -3265,7 +3265,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
 ; RV64ZICOND-NEXT:    czero.nez s1, a1, a0
 ; RV64ZICOND-NEXT:  .LBB55_1: # %bb2
 ; RV64ZICOND-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64ZICOND-NEXT:    sext.w a0, s1
+; RV64ZICOND-NEXT:    mv a0, s1
 ; RV64ZICOND-NEXT:    call bar at plt
 ; RV64ZICOND-NEXT:    sllw s1, s1, s0
 ; RV64ZICOND-NEXT:    bnez a0, .LBB55_1