[llvm] 979e8ae - [AArch64] Check opcode before trying to extract register from operand
David Tellenbach via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 23 14:49:57 PDT 2023
Author: David Tellenbach
Date: 2023-08-23T14:46:31-07:00
New Revision: 979e8ae4fce64546c65d24864eedd8165bc9787b
URL: https://github.com/llvm/llvm-project/commit/979e8ae4fce64546c65d24864eedd8165bc9787b
DIFF: https://github.com/llvm/llvm-project/commit/979e8ae4fce64546c65d24864eedd8165bc9787b.diff
LOG: [AArch64] Check opcode before trying to extract register from operand
When matching FNEG patterns for the MachineCombiner we need to check for
opcodes first, before trying to extract a register from an operand.
Otherwise handling of instructions with non-register operands causes the
compiler to crash.
Differential Revision: https://reviews.llvm.org/D158473
Added:
llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
Modified:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 1a9b36a5ef9f30..995b3baac06fac 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5514,8 +5514,8 @@ static bool getFNEGPatterns(MachineInstr &Root,
auto Match = [&](unsigned Opcode, MachineCombinerPattern Pattern) -> bool {
MachineOperand &MO = Root.getOperand(1);
MachineInstr *MI = MRI.getUniqueVRegDef(MO.getReg());
- if (MI != nullptr && MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()) &&
- (MI->getOpcode() == Opcode) &&
+ if (MI != nullptr && (MI->getOpcode() == Opcode) &&
+ MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()) &&
Root.getFlag(MachineInstr::MIFlag::FmContract) &&
Root.getFlag(MachineInstr::MIFlag::FmNsz) &&
MI->getFlag(MachineInstr::MIFlag::FmContract) &&
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
new file mode 100644
index 00000000000000..6fe094cc6cbb4e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -0,0 +1,130 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple aarch64 -run-pass=machine-combiner -o - %s | FileCheck %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64"
+
+ @c = global double 0.000000e+00, align 8
+
+ define void @emit_fneg_with_non_register_operand(double %c) {
+ entry:
+ %0 = load double, ptr @c, align 8
+ %1 = tail call double asm sideeffect "", "=w,0"(double %0)
+ %2 = load double, ptr @c, align 8
+ %3 = tail call double asm sideeffect "", "=w,0"(double %2)
+ %fneg = fneg double %1
+ %cmp = fcmp oeq double %3, %fneg
+ br i1 %cmp, label %if.then, label %if.end
+
+ if.then: ; preds = %entry
+ tail call void @b(double noundef %1)
+ ret void
+
+ if.end: ; preds = %entry
+ ret void
+ }
+
+ declare void @b(double noundef)
+
+...
+---
+name: emit_fneg_with_non_register_operand
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHCatchret: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: fpr64, preferred-register: '' }
+ - { id: 1, class: fpr64, preferred-register: '' }
+ - { id: 2, class: fpr64, preferred-register: '' }
+ - { id: 3, class: fpr64, preferred-register: '' }
+ - { id: 4, class: fpr64, preferred-register: '' }
+ - { id: 5, class: fpr64, preferred-register: '' }
+ - { id: 6, class: gpr64common, preferred-register: '' }
+ - { id: 7, class: fpr64, preferred-register: '' }
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: true
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: emit_fneg_with_non_register_operand
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.2(0x30000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
+ ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
+ ; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
+ ; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
+ ; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
+ ; CHECK-NEXT: B %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.if.then:
+ ; CHECK-NEXT: $d0 = COPY [[COPY]]
+ ; CHECK-NEXT: TCRETURNdi @b, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.if.end:
+ ; CHECK-NEXT: RET_ReallyLR
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
+
+ %6:gpr64common = LOADgot target-flags(aarch64-got) @c
+ %3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
+ %0:fpr64 = COPY %2
+ %5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
+ %7:fpr64 = FNEGDr %2
+ nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr
+ Bcc 1, %bb.2, implicit $nzcv
+ B %bb.1
+
+ bb.1.if.then:
+ $d0 = COPY %0
+ TCRETURNdi @b, 0, csr_aarch64_aapcs, implicit $sp, implicit $d0
+
+ bb.2.if.end:
+ RET_ReallyLR
+
+...
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