[PATCH] D158673: [SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1241
+    setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
+    if (Subtarget.is64Bit())
+      setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
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Why do we need to handle i32 on RV64? Wouldn't it be enough to do XLenLLT and remove the change to ReplaceNodeResults?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158673/new/

https://reviews.llvm.org/D158673