[PATCH] D158673: [SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D158673#4611704 <https://reviews.llvm.org/D158673#4611704>, @jrtc27 wrote:

> This seems like it would be better as a DAG->DAG transform pre-lowering? Or perhaps a more general peephole to merge the neg(w)+li? Or do it in TableGen? I don't think this warrants custom C++ //lowering//.

The isel patterns are creating the neg, it does seem better to create that early before isel to give maximum opportunity to combine it. The code in this patch seems very similar to AArch64.


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