[llvm] d6639f8 - [SDAG][RISCV] Avoid folding `setcc (xor C1, -1), C2, cond` into `setcc (xor C2, -1), C1, cond`
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 23 13:20:45 PDT 2023
Author: Yingwei Zheng
Date: 2023-08-24T04:18:17+08:00
New Revision: d6639f83a98f29275d4ae490d2962c1ec1d298a5
URL: https://github.com/llvm/llvm-project/commit/d6639f83a98f29275d4ae490d2962c1ec1d298a5
DIFF: https://github.com/llvm/llvm-project/commit/d6639f83a98f29275d4ae490d2962c1ec1d298a5.diff
LOG: [SDAG][RISCV] Avoid folding `setcc (xor C1, -1), C2, cond` into `setcc (xor C2, -1), C1, cond`
This patch fixes https://github.com/llvm/llvm-project/issues/64935.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D158654
Added:
llvm/test/CodeGen/RISCV/pr64935.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 31b1b39b34e575..e9bd516fecdd94 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5093,7 +5093,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (isBitwiseNot(N1))
return DAG.getSetCC(dl, VT, N1.getOperand(0), N0.getOperand(0), Cond);
- if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
+ if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
+ !DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(0))) {
SDValue Not = DAG.getNOT(dl, N1, OpVT);
return DAG.getSetCC(dl, VT, Not, N0.getOperand(0), Cond);
}
diff --git a/llvm/test/CodeGen/RISCV/pr64935.ll b/llvm/test/CodeGen/RISCV/pr64935.ll
new file mode 100644
index 00000000000000..60be5fa6c994e5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr64935.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
+
+define i1 @f() {
+; CHECK-LABEL: f:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: sltiu a0, a0, 2
+; CHECK-NEXT: xori a0, a0, 1
+; CHECK-NEXT: ret
+ %B25 = shl i64 4294967296, -9223372036854775808
+ %B13 = sub i64 -1, -9223372036854775808
+ %C8 = icmp ugt i64 %B13, %B25
+ %B5 = sub i64 0, 4294967296 ; Don't remove this instruction!
+ ret i1 %C8
+}
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