[llvm] 06d3ee9 - [RISCV] Fix wrong operand being used for VL in shift combine

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-08-23T17:44:21+01:00
New Revision: 06d3ee9603b60c642e2e70c4abc8b2f6d2322855

URL: https://github.com/llvm/llvm-project/commit/06d3ee9603b60c642e2e70c4abc8b2f6d2322855
DIFF: https://github.com/llvm/llvm-project/commit/06d3ee9603b60c642e2e70c4abc8b2f6d2322855.diff

LOG: [RISCV] Fix wrong operand being used for VL in shift combine

At some point a merge operand was added to the binary vl ops, so this combine
was using the mask for the VL. This causes a crash when trying to
select the vmv_v_x_vl, which showed up locally when messing about with
selectVSplat, but thankfully in ToT the vmv_v_x_vl gets pattern matched
away into the .vx and .vi operands every time, so there's no noticeable
change.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158634

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e9b528087d7135..4a855a9425ae3d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13730,7 +13730,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
       // We don't need the upper 32 bits of a 64-bit element for a shift amount.
       SDLoc DL(N);
-      SDValue VL = N->getOperand(3);
+      SDValue VL = N->getOperand(4);
       EVT VT = N->getValueType(0);
       ShAmt = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, DAG.getUNDEF(VT),
                           ShAmt.getOperand(1), VL);