[PATCH] D158634: [RISCV] Fix wrong operand being used for VL in shift combine

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:13455
   case RISCVISD::SHL_VL: {
     SDValue ShAmt = N->getOperand(1);
     if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
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Not specific to this patch, but I think with D158625 this combine might be doing the same thing as SimplifyDemanded. I.e. SimplifyDemanded has the ability to mark the upper hi bits of a build_pair as undef in a rotr/rotl (but this only seems to work on fixed vectors currently)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158634/new/

https://reviews.llvm.org/D158634