[PATCH] D158625: [RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts

[Luke Lau via Phabricator via llvm-commits]

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When lowering a splat_vector_parts, if the hi bits are undefined then we can
splat the lo bits without having to check if it's going to be sign extended or
not, because those bits will be undefined anyway.

I've handled it for both fixed and scalable vectors, but there's no diff 
on the scalable vror tests, since the hi bits aren't combined away to 
undef in SimplifyDemanded for scalable vectors. I'm not sure why that is.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158625

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

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