[llvm] 0d2fb9c - [ARM] Add the Arm Cortex-M85 scheduling model
Samuel Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 23 06:17:10 PDT 2023
Author: Samuel Tebbs
Date: 2023-08-23T14:15:34+01:00
New Revision: 0d2fb9c02bec8e553db715e177c796fb7317d9be
URL: https://github.com/llvm/llvm-project/commit/0d2fb9c02bec8e553db715e177c796fb7317d9be
DIFF: https://github.com/llvm/llvm-project/commit/0d2fb9c02bec8e553db715e177c796fb7317d9be.diff
LOG: [ARM] Add the Arm Cortex-M85 scheduling model
This patch adds a scheduling model for the Arm Cortex-M85 CPU and is based on the Software Optimisation Guide made available at https://developer.arm.com/documentation/107950/0100.
The model was written by David Penry.
Differential Revision: https://reviews.llvm.org/D158498
Added:
llvm/lib/Target/ARM/ARMScheduleM85.td
llvm/test/tools/llvm-mca/ARM/m85-fp.s
llvm/test/tools/llvm-mca/ARM/m85-int.s
llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s
llvm/test/tools/llvm-mca/ARM/m85-mve-int.s
llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s
Modified:
llvm/lib/Target/ARM/ARM.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 4bb20271d0f28b..bf64ecf6496447 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -1227,6 +1227,7 @@ include "ARMScheduleA57.td"
include "ARMScheduleM4.td"
include "ARMScheduleM55.td"
include "ARMScheduleM7.td"
+include "ARMScheduleM85.td"
//===----------------------------------------------------------------------===//
// ARM processors
@@ -1511,7 +1512,7 @@ def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline,
HasMVEFloatOps,
FeatureFixCMSE_CVE_2021_35465]>;
-def : ProcessorModel<"cortex-m85", CortexM7Model, [ARMv81mMainline,
+def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline,
FeatureDSP,
FeatureFPARMv8_D16,
FeaturePACBTI,
diff --git a/llvm/lib/Target/ARM/ARMScheduleM85.td b/llvm/lib/Target/ARM/ARMScheduleM85.td
new file mode 100644
index 00000000000000..0202e4ad4e5f9b
--- /dev/null
+++ b/llvm/lib/Target/ARM/ARMScheduleM85.td
@@ -0,0 +1,981 @@
+//=- ARMScheduleM85.td - ARM Cortex-M85 Scheduling Definitions -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for the ARM Cortex-M85 processor.
+//
+// All timing is referred to EX2. Thus, operands which are needed at EX1 are
+// stated to have a ReadAdvance of -1. The FP/MVE pipe actually begins at EX3
+// but is described as if it were in EX2 to avoid having unnaturally long latencies
+// with delayed inputs on every instruction. Instead, whenever an FP instruction
+// must access a GP register or a non-FP instruction (which includes loads/stores)
+// must access an FP register, the operand timing is adjusted:
+// FP accessing GPR: read one cycle later, write one cycle later
+// NOTE: absolute spec timing already includes this if
+// referenced to EX2
+// non-FP accessing FPR: read one cycle earlier, write one cycle earlier
+//===----------------------------------------------------------------------===//
+
+def CortexM85Model : SchedMachineModel {
+ let IssueWidth = 2; // Dual issue for most instructions.
+ let MicroOpBufferSize = 0; // M85 is in-order.
+ let LoadLatency = 2; // Best case for load-use case.
+ let MispredictPenalty = 4; // Mispredict cost for forward branches is 7,
+ // but 4 works better
+ let CompleteModel = 0;
+}
+
+let SchedModel = CortexM85Model in {
+
+//===--------------------------------------------------------------------===//
+// CortexM85 has two ALU, two LOAD, two STORE, a MAC, a BRANCH and two VFP
+// pipes (with three units). There are three shifters available: one per
+// stage.
+
+def M85UnitLoadL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitLoadH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitLoad : ProcResGroup<[M85UnitLoadL,M85UnitLoadH]> { let BufferSize = 0; }
+def M85UnitStoreL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitStoreH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitStore : ProcResGroup<[M85UnitStoreL,M85UnitStoreH]> { let BufferSize = 0; }
+def M85UnitALU : ProcResource<2> { let BufferSize = 0; }
+def M85UnitShift1 : ProcResource<1> { let BufferSize = 0; }
+def M85UnitShift2 : ProcResource<1> { let BufferSize = 0; }
+def M85UnitMAC : ProcResource<1> { let BufferSize = 0; }
+def M85UnitBranch : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPAL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPAH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPA : ProcResGroup<[M85UnitVFPAL,M85UnitVFPAH]> { let BufferSize = 0; }
+def M85UnitVFPBL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPBH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPB : ProcResGroup<[M85UnitVFPBL,M85UnitVFPBH]> { let BufferSize = 0; }
+def M85UnitVFPCL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPCH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVFPC : ProcResGroup<[M85UnitVFPCL,M85UnitVFPCH]> { let BufferSize = 0; }
+def M85UnitVFPD : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVPortL : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVPortH : ProcResource<1> { let BufferSize = 0; }
+def M85UnitVPort : ProcResGroup<[M85UnitVPortL,M85UnitVPortH]> { let BufferSize = 0; }
+def M85UnitSIMD : ProcResource<1> { let BufferSize = 0; }
+def M85UnitLShift : ProcResource<1> { let BufferSize = 0; }
+def M85UnitDiv : ProcResource<1> { let BufferSize = 0; }
+
+def M85UnitSlot0 : ProcResource<1> { let BufferSize = 0; }
+
+//===---------------------------------------------------------------------===//
+// Subtarget-specific SchedWrite types with map ProcResources and set latency.
+
+def : WriteRes<WriteALU, [M85UnitALU]> { let Latency = 1; }
+
+// Basic ALU with shifts.
+let Latency = 1 in {
+ def : WriteRes<WriteALUsi, [M85UnitALU, M85UnitShift1]>;
+ def : WriteRes<WriteALUsr, [M85UnitALU, M85UnitShift1]>;
+ def : WriteRes<WriteALUSsr, [M85UnitALU, M85UnitShift1]>;
+}
+
+// Compares.
+def : WriteRes<WriteCMP, [M85UnitALU]> { let Latency = 1; }
+def : WriteRes<WriteCMPsi, [M85UnitALU, M85UnitShift1]> { let Latency = 2; }
+def : WriteRes<WriteCMPsr, [M85UnitALU, M85UnitShift1]> { let Latency = 2; }
+
+// Multiplies.
+let Latency = 2 in {
+ def : WriteRes<WriteMUL16, [M85UnitMAC]>;
+ def : WriteRes<WriteMUL32, [M85UnitMAC]>;
+ def : WriteRes<WriteMUL64Lo, [M85UnitMAC]>;
+ def : WriteRes<WriteMUL64Hi, []> { let NumMicroOps = 0; }
+}
+
+// Multiply-accumulates.
+let Latency = 2 in {
+def : WriteRes<WriteMAC16, [M85UnitMAC]>;
+def : WriteRes<WriteMAC32, [M85UnitMAC]>;
+def : WriteRes<WriteMAC64Lo, [M85UnitMAC]>;
+def : WriteRes<WriteMAC64Hi, []> { let NumMicroOps = 0; }
+}
+
+// Divisions.
+def : WriteRes<WriteDIV, [M85UnitDiv]> {
+ let Latency = 7;
+}
+
+// Loads/Stores.
+def : WriteRes<WriteLd, [M85UnitLoad]> { let Latency = 1; }
+def : WriteRes<WritePreLd, [M85UnitLoad]> { let Latency = 2; }
+def : WriteRes<WriteST, [M85UnitStore]> { let Latency = 2; }
+def M85WriteLdWide : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH]> { let Latency = 1; }
+def M85WriteStWide : SchedWriteRes<[M85UnitStoreL, M85UnitStoreH]> { let Latency = 2; }
+
+// Branches.
+def : WriteRes<WriteBr, [M85UnitBranch]> { let Latency = 2; }
+def : WriteRes<WriteBrL, [M85UnitBranch]> { let Latency = 2; }
+def : WriteRes<WriteBrTbl, [M85UnitBranch]> { let Latency = 2; }
+
+// Noop.
+def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for floating-point instructions
+//
+// Floating point conversions.
+def : WriteRes<WriteFPCVT, [M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 2;
+}
+def : WriteRes<WriteFPMOV, [M85UnitVPort, M85UnitSlot0]> { let Latency = 1; }
+def M85WriteFPMOV64 : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> { let Latency = 1; }
+
+// ALU operations (32/64-bit). These go down the FP pipeline.
+def : WriteRes<WriteFPALU32, [M85UnitVFPA, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 2;
+}
+def : WriteRes<WriteFPALU64, [M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let Latency = 6;
+}
+
+// Multiplication
+def : WriteRes<WriteFPMUL32, [M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 3;
+}
+def : WriteRes<WriteFPMUL64, [M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let Latency = 8;
+}
+
+// Multiply-accumulate. FPMAC goes down the FP Pipeline.
+def : WriteRes<WriteFPMAC32, [M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 5;
+}
+def : WriteRes<WriteFPMAC64, [M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let Latency = 14;
+}
+
+// Division. Effective scheduling latency is 3, though real latency is larger
+def : WriteRes<WriteFPDIV32, [M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 14;
+}
+def : WriteRes<WriteFPDIV64, [M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let Latency = 29;
+}
+
+// Square-root. Effective scheduling latency is 3, though real latency is larger
+def : WriteRes<WriteFPSQRT32, [M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 14;
+}
+def : WriteRes<WriteFPSQRT64, [M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let Latency = 29;
+}
+
+let NumMicroOps = 0 in {
+ def M85SingleIssue : SchedWriteRes<[]> { let SingleIssue = 1; }
+ def M85Slot0Only : SchedWriteRes<[M85UnitSlot0]> { }
+}
+
+// What pipeline stage operands need to be ready for depending on
+// where they come from.
+def : ReadAdvance<ReadALUsr, 0>;
+def : ReadAdvance<ReadMUL, 0>;
+def : ReadAdvance<ReadMAC, 1>;
+def : ReadAdvance<ReadALU, 0>;
+def : ReadAdvance<ReadFPMUL, 0>;
+def : ReadAdvance<ReadFPMAC, 3>;
+def M85Read_ISSm1 : SchedReadAdvance<-2>; // operands needed at ISS
+def M85Read_ISS : SchedReadAdvance<-1>; // operands needed at EX1
+def M85Read_EX1 : SchedReadAdvance<0>; // operands needed at EX2
+def M85Read_EX2 : SchedReadAdvance<1>; // operands needed at EX3
+def M85Read_EX3 : SchedReadAdvance<2>; // operands needed at EX4
+def M85Read_EX4 : SchedReadAdvance<3>; // operands needed at EX5
+def M85Write1 : SchedWriteRes<[]> {
+ let Latency = 1;
+ let NumMicroOps = 0;
+}
+def M85Write2 : SchedWriteRes<[]> {
+ let Latency = 2;
+ let NumMicroOps = 0;
+}
+def M85WriteShift2 : SchedWriteRes<[M85UnitALU, M85UnitShift2]> {}
+
+// Non general purpose instructions may not be dual issued. These
+// use both issue units.
+def M85NonGeneralPurpose : SchedWriteRes<[]> {
+ // Assume that these will go down the main ALU pipeline.
+ // In reality, many look likely to stall the whole pipeline.
+ let Latency = 3;
+ let SingleIssue = 1;
+}
+
+// List the non general purpose instructions.
+def : InstRW<[M85NonGeneralPurpose],
+ (instregex "t2MRS", "tSVC", "tBKPT", "t2MSR", "t2DMB", "t2DSB",
+ "t2ISB", "t2HVC", "t2SMC", "t2UDF", "ERET", "tHINT",
+ "t2HINT", "t2CLREX", "t2CLRM", "BUNDLE")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for load/store
+//
+// Mark whether the loads/stores must be single-issue
+// Address operands are needed earlier
+// Data operands are needed later
+
+let NumMicroOps = 0 in {
+ def M85BaseUpdate : SchedWriteRes<[]> {
+ // Update is bypassable out of EX1
+ let Latency = 0;
+ }
+ def M85MVERBaseUpdate : SchedWriteRes<[]> { let Latency = 1; }
+ // Q register base update is available in EX3 to bypass into EX2/ISS.
+ // Latency=2 matches what we want for ISS, Latency=1 for EX2. Going
+ // with 2, as base update into another load/store is most likely. Could
+ // change later in an override.
+ def M85MVEQBaseUpdate : SchedWriteRes<[]> { let Latency = 2; }
+ def M85LoadLatency1 : SchedWriteRes<[]> { let Latency = 1; }
+}
+def M85SlowLoad : SchedWriteRes<[M85UnitLoad]> { let Latency = 2; }
+
+// Byte and half-word loads should have greater latency than other loads.
+// So should load exclusive?
+
+def : InstRW<[M85SlowLoad],
+ (instregex "t2LDR(B|H|SB|SH)pc")>;
+def : InstRW<[M85SlowLoad, M85Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)T", "t2LDR(B|H|SB|SH)i",
+ "tLDRspi", "tLDR(B|H)i")>;
+def : InstRW<[M85SlowLoad, M85Read_ISS, M85Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)s")>;
+def : InstRW<[M85SlowLoad, M85Read_ISS, M85Read_ISS],
+ (instregex "tLDR(B|H)r", "tLDR(SB|SH)")>;
+def : InstRW<[M85SlowLoad, M85BaseUpdate, M85Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)_(POST|PRE)")>;
+
+// Exclusive/acquire/release loads/stores cannot be dual-issued
+def : InstRW<[WriteLd, M85SingleIssue, M85Read_ISS],
+ (instregex "t2LDREX$", "t2LDA(EX)?$")>;
+def : InstRW<[M85WriteLdWide, M85LoadLatency1, M85SingleIssue, M85Read_ISS],
+ (instregex "t2LDAEXD$")>;
+def : InstRW<[M85SlowLoad, M85SingleIssue, M85Read_ISS],
+ (instregex "t2LDREX(B|H)", "t2LDA(EX)?(B|H)$")>;
+def : InstRW<[WriteST, M85SingleIssue, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STREX(B|H)?$", "t2STL(EX)?(B|H)?$")>;
+def : InstRW<[M85WriteStWide, M85SingleIssue, M85Read_EX2, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STLEXD$")>;
+
+// Load/store multiples end issue groups.
+
+def : InstRW<[M85WriteLdWide, M85SingleIssue, M85Read_ISS],
+ (instregex "(t|t2)LDM(DB|IA)$")>;
+def : InstRW<[M85WriteStWide, M85SingleIssue, M85Read_ISS],
+ (instregex "(t|t2)STM(DB|IA)$")>;
+def : InstRW<[M85BaseUpdate, M85WriteLdWide, M85SingleIssue, M85Read_ISS],
+ (instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
+def : InstRW<[M85BaseUpdate, M85WriteStWide, M85SingleIssue, M85Read_ISS],
+ (instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>;
+
+// Load/store doubles
+
+def : InstRW<[M85BaseUpdate, M85WriteStWide,
+ M85Read_EX2, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STRD_(PRE|POST)")>;
+def : InstRW<[M85WriteStWide, M85Read_EX2, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STRDi")>;
+def : InstRW<[M85WriteLdWide, M85LoadLatency1, M85BaseUpdate, M85Read_ISS],
+ (instregex "t2LDRD_(PRE|POST)")>;
+def : InstRW<[M85WriteLdWide, M85LoadLatency1, M85Read_ISS],
+ (instregex "t2LDRDi")>;
+
+// Word load / preload
+def : InstRW<[WriteLd],
+ (instregex "t2LDRpc", "t2PL[DI]pci", "tLDRpci")>;
+def : InstRW<[WriteLd, M85Read_ISS],
+ (instregex "t2LDR(i|T)", "t2PL[DI](W)?i", "tLDRi")>;
+def : InstRW<[WriteLd, M85Read_ISS, M85Read_ISS],
+ (instregex "t2LDRs", "t2PL[DI](w)?s", "tLDRr")>;
+def : InstRW<[WriteLd, M85BaseUpdate, M85Read_ISS],
+ (instregex "t2LDR_(POST|PRE)")>;
+
+// Stores
+def : InstRW<[M85BaseUpdate, WriteST, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STR(B|H)?_(POST|PRE)")>;
+def : InstRW<[WriteST, M85Read_EX2, M85Read_ISS, M85Read_ISS],
+ (instregex "t2STR(B|H)?s$", "tSTR(B|H)?r$")>;
+def : InstRW<[WriteST, M85Read_EX2, M85Read_ISS],
+ (instregex "t2STR(B|H)?(i|T)", "tSTR(B|H)?i$", "tSTRspi")>;
+
+// TBB/TBH - single-issue only
+
+def M85TableLoad : SchedWriteRes<[M85UnitLoad]> { let SingleIssue = 1; }
+
+def : InstRW<[M85TableLoad, M85Read_ISS, M85Read_ISS],
+ (instregex "t2TB")>;
+
+// VFP/MVE loads and stores
+// Note: timing for VLDR/VSTR special has not been broken out
+// Note 2: see notes at top of file for the reason load latency is 1 and
+// store data is in EX3.
+
+def M85LoadSP : SchedWriteRes<[M85UnitLoad, M85UnitVPort]>;
+def M85LoadDP : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
+ M85UnitVPortL, M85UnitVPortH]>;
+def M85LoadSys : SchedWriteRes<[M85UnitLoad, M85UnitVPort,
+ M85UnitVFPA, M85UnitVFPB, M85UnitVFPC, M85UnitVFPD]> {
+ let Latency = 4;
+}
+def M85StoreSP : SchedWriteRes<[M85UnitStore, M85UnitVPort]>;
+def M85StoreDP : SchedWriteRes<[M85UnitStoreL, M85UnitStoreH,
+ M85UnitVPortL, M85UnitVPortH]>;
+def M85StoreSys : SchedWriteRes<[M85UnitStore, M85UnitVPort,
+ M85UnitVFPA, M85UnitVFPB, M85UnitVFPC, M85UnitVFPD]>;
+let ResourceCycles = [2,2,1,1], EndGroup = 1 in {
+ def M85LoadMVE : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
+ M85UnitVPortL, M85UnitVPortH]>;
+ def M85LoadMVELate : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
+ M85UnitVPortL, M85UnitVPortH]> {
+ let Latency = 4; // 3 cycles later
+ }
+ def M85StoreMVE : SchedWriteRes<[M85UnitStoreL, M85UnitStoreH,
+ M85UnitVPortL, M85UnitVPortH]>;
+}
+
+def : InstRW<[M85LoadSP, M85Read_ISS], (instregex "VLDR(S|H)$")>;
+def : InstRW<[M85LoadSys, M85Read_ISS], (instregex "VLDR_")>;
+def : InstRW<[M85LoadDP, M85Read_ISS], (instregex "VLDRD$")>;
+def : InstRW<[M85StoreSP, M85Read_EX3, M85Read_ISS], (instregex "VSTR(S|H)$")>;
+def : InstRW<[M85StoreSys, M85Read_EX1, M85Read_ISS], (instregex "VSTR_")>;
+def : InstRW<[M85StoreDP, M85Read_EX3, M85Read_ISS], (instregex "VSTRD$")>;
+
+def : InstRW<[M85LoadMVELate, M85Read_ISS],
+ (instregex "MVE_VLD[24]._[0-9]+$")>;
+def : InstRW<[M85LoadMVELate, M85MVERBaseUpdate, M85Read_ISS],
+ (instregex "MVE_VLD[24].*wb")>;
+def : InstRW<[M85LoadMVE, M85Read_ISS],
+ (instregex "MVE_VLDR.*(8|16|32|64)$")>;
+def : InstRW<[M85LoadMVE, M85SingleIssue, M85Read_ISS, M85Read_ISS],
+ (instregex "MVE_VLDR.*(_rq|_rq|_rq_u)$")>;
+def : InstRW<[M85LoadMVE, M85SingleIssue, M85Read_ISS],
+ (instregex "MVE_VLDR.*_qi$")>;
+def : InstRW<[M85MVERBaseUpdate, M85LoadMVE, M85Read_ISS],
+ (instregex "MVE_VLDR.*(_post|[^i]_pre)$")>;
+def : InstRW<[M85MVEQBaseUpdate, M85SingleIssue, M85LoadMVE, M85Read_ISS],
+ (instregex "MVE_VLDR.*(qi_pre)$")>;
+
+def : InstRW<[M85StoreMVE, M85Read_EX3, M85Read_ISS],
+ (instregex "MVE_VST[24]._[0-9]+$")>;
+def : InstRW<[M85StoreMVE, M85Read_EX3, M85MVERBaseUpdate, M85Read_ISS],
+ (instregex "MVE_VST[24].*wb")>;
+def : InstRW<[M85StoreMVE, M85Read_EX3, M85Read_ISS],
+ (instregex "MVE_VSTR.*(8|16|32|64)$")>;
+def : InstRW<[M85StoreMVE, M85SingleIssue, M85Read_EX3, M85Read_ISS, M85Read_ISS],
+ (instregex "MVE_VSTR.*(_rq|_rq|_rq_u)$")>;
+def : InstRW<[M85StoreMVE, M85SingleIssue, M85Read_EX3, M85Read_ISS],
+ (instregex "MVE_VSTR.*_qi$")>;
+def : InstRW<[M85MVERBaseUpdate, M85StoreMVE, M85Read_EX3, M85Read_ISS],
+ (instregex "MVE_VSTR.*(_post|[^i]_pre)$")>;
+def : InstRW<[M85MVEQBaseUpdate, M85SingleIssue, M85StoreMVE,
+ M85Read_EX3, M85Read_ISS],
+ (instregex "MVE_VSTR.*(qi_pre)$")>;
+
+// Load/store multiples end issue groups.
+
+def : InstRW<[M85WriteLdWide, M85SingleIssue, M85Read_ISS],
+ (instregex "VLDM(S|D|Q)(DB|IA)$")>;
+def : InstRW<[M85WriteStWide, M85SingleIssue, M85Read_ISS, M85Read_EX3],
+ (instregex "VSTM(S|D|Q)(DB|IA)$")>;
+def : InstRW<[M85BaseUpdate, M85WriteLdWide, M85SingleIssue, M85Read_ISS],
+ (instregex "VLDM(S|D|Q)(DB|IA)_UPD$", "VLLDM")>;
+def : InstRW<[M85BaseUpdate, M85WriteStWide, M85SingleIssue,
+ M85Read_ISS, M85Read_EX3],
+ (instregex "VSTM(S|D|Q)(DB|IA)_UPD$", "VLSTM")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for ALU
+//
+
+// Non-small shifted ALU operands are read a cycle early; small LSLs
+// aren't, as they don't require the shifter.
+
+def M85NonsmallShiftWrite : SchedWriteRes<[M85UnitALU,M85UnitShift1]> {
+ let Latency = 1;
+}
+
+def M85WriteALUsi : SchedWriteVariant<[
+ SchedVar<NoSchedPred, [M85NonsmallShiftWrite]>
+]>;
+def M85Ex1ReadNoFastBypass : SchedReadAdvance<-1,
+ [WriteLd, M85WriteLdWide, M85LoadLatency1]>;
+def M85ReadALUsi : SchedReadVariant<[
+ SchedVar<NoSchedPred, [M85Read_ISS]>
+]>;
+
+def : InstRW<[M85WriteALUsi, M85Read_EX1, M85ReadALUsi],
+ (instregex "t2(ADC|ADDS|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|"
+ "SUBS|CMP|CMNz|TEQ|TST)rs$")>;
+def : InstRW<[M85WriteALUsi, M85ReadALUsi],
+ (instregex "t2MVNs")>;
+
+// CortexM85 treats LSL #0 as needing a shifter. In practice the throughput
+// seems to reliably be 2 when run on a cyclemodel, so we don't require a
+// shift resource.
+def : InstRW<[M85WriteALUsi, M85Read_EX1, M85ReadALUsi],
+ (instregex "t2(ADC|ADDS|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|"
+ "SUBS|CMP|CMNz|TEQ|TST)rr$")>;
+def : InstRW<[M85WriteALUsi, M85ReadALUsi],
+ (instregex "t2MVNr")>;
+
+// Shift instructions: most pure shifts (i.e. MOV w/ shift) will use whichever
+// shifter is free, thus it is possible to dual-issue them freely with anything
+// else. As a result, they are not modeled as needing a shifter.
+// RRX is odd because it must use the EX2 shifter, so it cannot dual-issue with
+// itself.
+//
+// Note that pure shifts which use the EX1 shifter would need their operands
+// a cycle earlier. However, they are only forced to use the EX1 shifter
+// when issuing against an RRX instructions, which should be rare.
+
+def : InstRW<[M85WriteShift2],
+ (instregex "t2RRX$")>;
+def : InstRW<[WriteALU],
+ (instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)", "t2MOVsr(a|l)")>;
+
+// Instructions that use the shifter, but have normal timing
+
+def : InstRW<[WriteALUsi,M85Slot0Only], (instregex "t2(BFC|BFI)$")>;
+
+// Stack pointer add/sub happens in EX1 with checks in EX2
+
+def M85WritesToSPPred : MCSchedPredicate<CheckRegOperand<0, SP>>;
+
+def M85ReadForSP : SchedReadVariant<[
+ SchedVar<M85WritesToSPPred, [M85Read_ISS]>,
+ SchedVar<NoSchedPred, [M85Read_EX1]>
+]>;
+def M85ReadForSPShift : SchedReadVariant<[
+ SchedVar<M85WritesToSPPred, [M85Read_ISS]>,
+ SchedVar<NoSchedPred, [M85Read_ISS]>
+]>;
+
+def : InstRW<[WriteALU, M85Read_ISS],
+ (instregex "tADDspi", "tSUBspi")>;
+def : InstRW<[WriteALU, M85ReadForSP],
+ (instregex "t2(ADD|SUB)ri", "t2MOVr", "tMOVr")>;
+def : InstRW<[WriteALU, M85ReadForSP, M85ReadForSP],
+ (instregex "tADDrSP", "tADDspr", "tADDhirr")>;
+def : InstRW<[M85WriteALUsi, M85ReadForSP, M85ReadForSPShift],
+ (instregex "t2(ADD|SUB)rs")>;
+
+def : InstRW<[WriteALU, M85Slot0Only], (instregex "t2CLZ")>;
+
+// MAC operations that don't have SchedRW set
+
+def : InstRW<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC], (instregex "t2SML[AS]D")>;
+
+// Divides are special because they stall for their latency, and so look like
+// two cycles as far as scheduling opportunities go. By putting M85Write2
+// first, we make the operand latency 2, but keep the instruction latency 7.
+// Divide operands are read early.
+
+def : InstRW<[M85Write2, WriteDIV, M85Read_ISS, M85Read_ISS, WriteALU],
+ (instregex "t2(S|U)DIV")>;
+
+// DSP extension operations
+
+def M85WriteSIMD1 : SchedWriteRes<[M85UnitSIMD, M85UnitALU, M85UnitSlot0]> {
+ let Latency = 1;
+}
+def M85WriteSIMD2 : SchedWriteRes<[M85UnitSIMD, M85UnitALU, M85UnitSlot0]> {
+ let Latency = 2;
+}
+def M85WriteShSIMD0 : SchedWriteRes<[M85UnitSIMD, M85UnitALU,
+ M85UnitShift1, M85UnitSlot0]> {
+ let Latency = 0; // Finishes at EX1
+}
+def M85WriteShSIMD1 : SchedWriteRes<[M85UnitSIMD, M85UnitALU,
+ M85UnitShift1, M85UnitSlot0]> {
+ let Latency = 1;
+}
+def M85WriteShSIMD2 : SchedWriteRes<[M85UnitSIMD, M85UnitALU,
+ M85UnitShift1, M85UnitSlot0]> {
+ let Latency = 2;
+}
+
+def : InstRW<[M85WriteShSIMD2, M85Read_ISS],
+ (instregex "t2(S|U)SAT")>;
+def : InstRW<[M85WriteSIMD1, ReadALU],
+ (instregex "(t|t2)(S|U)XT(B|H)")>;
+def : InstRW<[M85WriteSIMD1, ReadALU, ReadALU],
+ (instregex "t2(S|SH|U|UH)(ADD16|ADD8|ASX|SAX|SUB16|SUB8)",
+ "t2SEL")>;
+def : InstRW<[M85WriteSIMD2, ReadALU, ReadALU],
+ (instregex "t2(Q|UQ)(ADD|ASX|SAX|SUB)", "t2USAD8")>;
+def : InstRW<[M85WriteShSIMD2, M85Read_ISS, M85Read_ISS],
+ (instregex "t2QD(ADD|SUB)")>;
+def : InstRW<[M85WriteShSIMD0, M85Read_ISS],
+ (instregex "t2(RBIT|REV)", "tREV")>;
+def : InstRW<[M85WriteShSIMD1, ReadALU, M85Read_ISS],
+ (instregex "t2PKH(BT|TB)", "t2(S|U)XTA")>;
+def : InstRW<[M85WriteSIMD2, ReadALU, ReadALU, M85Read_EX2],
+ (instregex "t2USADA8")>;
+
+// MSR/MRS
+def : InstRW<[M85NonGeneralPurpose], (instregex "MSR", "MRS")>;
+
+// 64-bit shift operations in EX3
+
+def M85WriteLShift : SchedWriteRes<[M85UnitLShift, M85UnitALU]> {
+ let Latency = 2;
+}
+def M85WriteLat2 : SchedWriteRes<[]> { let Latency = 2; let NumMicroOps = 0; }
+
+def : InstRW<[M85WriteLShift, M85WriteLat2, M85Read_EX2, M85Read_EX2],
+ (instregex "MVE_(ASRLi|LSLLi|LSRL|SQSHLL|SRSHRL|UQSHLL|URSHRL)$")>;
+def : InstRW<[M85WriteLShift, M85WriteLat2,
+ M85Read_EX2, M85Read_EX2, M85Read_EX2],
+ (instregex "MVE_(ASRLr|LSLLr|SQRSHRL|UQRSHLL)$")>;
+def : InstRW<[M85WriteLShift, M85Read_EX2, M85Read_EX2],
+ (instregex "MVE_(SQRSHR|UQRSHL)$")>;
+def : InstRW<[M85WriteLShift, M85Read_EX2],
+ (instregex "MVE_(SQSHL|SRSHR|UQSHL|URSHR)$")>;
+
+// Loop control/branch future instructions
+
+def M85LE : SchedWriteRes<[]> { let NumMicroOps = 0; let Latency = -2; }
+
+def : InstRW<[WriteALU], (instregex "t2BF(_|Lr|i|Li|r)")>;
+
+def : InstRW<[WriteALU], (instregex "MVE_LCTP")>;
+def : InstRW<[WriteALU],
+ (instregex "t2DLS", "t2WLS", "MVE_DLSTP", "MVE_WLSTP")>;
+def : InstRW<[M85LE], (instregex "t2LE$")>;
+def : InstRW<[M85LE, M85Read_ISSm1],
+ (instregex "t2LEUpdate", "MVE_LETP")>; // LE is executed at ISS
+
+// Conditional selects
+
+def : InstRW<[M85WriteLShift, M85Read_EX2, M85Read_EX2, M85Read_EX2],
+ (instregex "t2(CSEL|CSINC|CSINV|CSNEG)")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for FP and MVE operations
+
+let NumMicroOps = 0 in {
+ def M85OverrideVFPLat5 : SchedWriteRes<[]> { let Latency = 5; }
+ def M85OverrideVFPLat4 : SchedWriteRes<[]> { let Latency = 4; }
+ def M85OverrideVFPLat3 : SchedWriteRes<[]> { let Latency = 3; }
+ def M85OverrideVFPLat2 : SchedWriteRes<[]> { let Latency = 2; }
+}
+
+let Latency = 1 in {
+ def M85GroupALat1S : SchedWriteRes<[M85UnitVFPA, M85UnitVPort, M85UnitSlot0]>;
+ def M85GroupBLat1S : SchedWriteRes<[M85UnitVFPB, M85UnitVPort, M85UnitSlot0]>;
+ def M85GroupCLat1S : SchedWriteRes<[M85UnitVFPC, M85UnitVPort, M85UnitSlot0]>;
+ def M85GroupALat1D : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GroupBLat1D : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GroupCLat1D : SchedWriteRes<[M85UnitVFPCL, M85UnitVFPCH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GroupABLat1S : SchedWriteRes<[M85UnitVPort, M85UnitSlot0]>;
+}
+let Latency = 2 in {
+ def M85GroupBLat2S : SchedWriteRes<[M85UnitVFPB, M85UnitVPort, M85UnitSlot0]>;
+ def M85GroupBLat2D : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GroupABLat2S : SchedWriteRes<[M85UnitVPort, M85UnitSlot0]>;
+ def M85GroupABLat2D : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+}
+
+// Instructions which are missing default schedules
+def : InstRW<[M85GroupALat1S], (instregex "V(FP_VMAXNM|FP_VMINNM)(H|S)$")>;
+def : InstRW<[M85GroupALat1D], (instregex "V(FP_VMAXNM|FP_VMINNM)D$")>;
+def : InstRW<[M85GroupCLat1S], (instregex "VCMPE?Z?(H|S)$")>;
+def : InstRW<[M85GroupCLat1D], (instregex "VCMPE?Z?D$")>;
+def : InstRW<[M85GroupBLat2S],
+ (instregex "VCVT(A|M|N|P|R|X|Z)(S|U)(H|S)",
+ "VRINT(A|M|N|P|R|X|Z)(H|S)")>;
+def : InstRW<[M85GroupBLat2D],
+ (instregex "VCVT(B|T)(DH|HD)", "VCVT(A|M|N|P|R|X|Z)(S|U)D",
+ "V.*TOD", "VTO.*D", "VCVTDS", "VCVTSD",
+ "VRINT(A|M|N|P|R|X|Z)D")>;
+def : InstRW<[M85GroupABLat1S], (instregex "VINSH")>;
+def : InstRW<[M85GroupBLat1S], (instregex "V(ABS|NEG)(H|S)$")>;
+def : InstRW<[M85GroupBLat1D], (instregex "V(ABS|NEG)D$")>;
+
+// VMRS/VMSR
+let SingleIssue = 1 in {
+ def M85VMRSEarly : SchedWriteRes<[M85UnitVPort]> { let Latency = 2;}
+ def M85VMRSLate : SchedWriteRes<[M85UnitVPort]> { let Latency = 4; }
+ def M85VMSREarly : SchedWriteRes<[M85UnitVPort]> { let Latency = 1; }
+ def M85VMSRLate : SchedWriteRes<[M85UnitVPort]> { let Latency = 3; }
+}
+
+def M85FPSCRFlagPred : MCSchedPredicate<
+ CheckAll<[CheckIsRegOperand<0>,
+ CheckRegOperand<0, PC>]>>;
+
+def M85VMRSFPSCR : SchedWriteVariant<[
+ SchedVar<M85FPSCRFlagPred, [M85VMRSEarly]>,
+ SchedVar<NoSchedPred, [M85VMRSLate]>
+]>;
+
+def : InstRW<[M85VMSREarly, M85Read_EX2],
+ (instregex "VMSR$", "VMSR_FPSCR_NZCVQC", "VMSR_P0", "VMSR_VPR")>;
+def : InstRW<[M85VMRSEarly], (instregex "VMRS_P0", "VMRS_VPR", "FMSTAT")>;
+def : InstRW<[M85VMRSLate], (instregex "VMRS_FPSCR_NZCVQC")>;
+def : InstRW<[M85VMRSFPSCR], (instregex "VMRS$")>;
+// Not matching properly
+//def : InstRW<[M85VMSRLate, M85Read_EX2], (instregex "VMSR_FPCTX(NS|S)")>;
+//def : InstRW<[M85VMRSLate], (instregex "VMRS_FPCTX(NS|S)")>;
+
+// VSEL cannot bypass in its implied $cpsr operand; model as earlier read
+def : InstRW<[M85GroupBLat1S, ReadALU, ReadALU, M85Read_ISS],
+ (instregex "VSEL.*(S|H)$")>;
+def : InstRW<[M85GroupBLat1D, ReadALU, ReadALU, M85Read_ISS],
+ (instregex "VSEL.*D$")>;
+
+// VMOV
+def : InstRW<[WriteFPMOV],
+ (instregex "VMOV(H|S)$", "FCONST(H|S)")>;
+def : InstRW<[WriteFPMOV, M85Read_EX2],
+ (instregex "VMOVHR$", "VMOVSR$")>;
+def : InstRW<[M85GroupABLat2S],
+ (instregex "VMOVRH$", "VMOVRS$")>;
+def : InstRW<[M85WriteFPMOV64],
+ (instregex "VMOVD$")>;
+def : InstRW<[M85WriteFPMOV64],
+ (instregex "FCONSTD")>;
+def : InstRW<[M85WriteFPMOV64, M85Read_EX2, M85Read_EX2],
+ (instregex "VMOVDRR")>;
+def : InstRW<[M85WriteFPMOV64, M85Write1, M85Read_EX2, M85Read_EX2],
+ (instregex "VMOVSRR")>;
+def : InstRW<[M85GroupABLat2D, M85Write2],
+ (instregex "VMOV(RRD|RRS)")>;
+
+// These shouldn't even exist, but Cortex-m55 defines them, so here they are.
+def : InstRW<[WriteFPMOV, M85Read_EX2],
+ (instregex "VGETLNi32$")>;
+def : InstRW<[M85GroupABLat2S],
+ (instregex "VSETLNi32")>;
+
+// Larger-latency overrides
+
+def M85FPDIV16 : SchedWriteRes<[M85UnitVFPB, M85UnitVPort, M85UnitSlot0]> {
+ let Latency = 8;
+}
+def : InstRW<[M85OverrideVFPLat2, M85FPDIV16], (instregex "VDIVH")>;
+def : InstRW<[M85OverrideVFPLat2, WriteFPDIV32], (instregex "VDIVS")>;
+def : InstRW<[M85OverrideVFPLat2, WriteFPDIV64], (instregex "VDIVD")>;
+def : InstRW<[M85OverrideVFPLat2, M85FPDIV16], (instregex "VSQRTH")>;
+def : InstRW<[M85OverrideVFPLat2, WriteFPSQRT32], (instregex "VSQRTS")>;
+def : InstRW<[M85OverrideVFPLat2, WriteFPSQRT64], (instregex "VSQRTD")>;
+def : InstRW<[M85OverrideVFPLat3, WriteFPMUL64], (instregex "V(MUL|NMUL)D")>;
+def : InstRW<[M85OverrideVFPLat2, WriteFPALU64], (instregex "V(ADD|SUB)D")>;
+
+// Multiply-accumulate. Chained SP timing is correct; rest need overrides
+// Double-precision chained MAC should also be seen as having latency of 5,
+// as stalls stall everything.
+
+def : InstRW<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL],
+ (instregex "VN?ML(A|S)H")>;
+
+def : InstRW<[M85OverrideVFPLat5, WriteFPMAC64,
+ ReadFPMUL, ReadFPMUL, ReadFPMUL],
+ (instregex "VN?ML(A|S)D$")>;
+
+// Single-precision fused MACs look like latency 4 with advance of 2.
+
+def M85ReadFPMAC2 : SchedReadAdvance<2>;
+
+def : InstRW<[M85OverrideVFPLat4, WriteFPMAC32,
+ M85ReadFPMAC2, ReadFPMUL, ReadFPMUL],
+ (instregex "VF(N)?M(A|S)(H|S)$")>;
+
+// Double-precision fused MAC looks like latency 4.
+
+def : InstRW<[M85OverrideVFPLat4, WriteFPMAC64,
+ ReadFPMUL, ReadFPMUL, ReadFPMUL],
+ (instregex "VF(N)?M(A|S)D$")>;
+
+// MVE beatwise instructions
+// NOTE: Q-register timing for the 2nd beat is off by a cycle and needs
+// DAG overrides to correctly set latencies.
+// NOTE2: MVE integer MAC->MAC accumulate latencies are set as if the
+// accumulate value arrives from an unmatching MAC instruction;
+// matching ones are handled via DAG mutation. These are marked as
+// "limited accumulate bypass"
+
+let Latency = 4, EndGroup = 1 in {
+ def M85GrpALat2MveR : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpABLat2MveR : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GrpBLat2MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85Lat2MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
+ def M85GrpBLat4Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+}
+let Latency = 3, EndGroup = 1 in {
+ def M85GrpBLat3Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpBLat1MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85Lat1MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
+}
+let Latency = 2, EndGroup = 1 in {
+ def M85GrpALat2Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpABLat2Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GrpBLat2Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85Lat2Mve : SchedWriteRes<[]> { let NumMicroOps = 0; }
+}
+let Latency = 1, EndGroup = 1 in {
+ def M85GrpALat1Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpABLat1Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
+ def M85GrpBLat1Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpCLat1Mve : SchedWriteRes<[M85UnitVFPCL, M85UnitVFPCH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,2,1,1,1];
+ }
+ def M85GrpDLat1Mve : SchedWriteRes<[M85UnitVFPD, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
+ let ResourceCycles = [2,1,1,1];
+ }
+}
+
+def : InstRW<[M85GrpABLat1Mve, M85Read_EX1, M85Read_EX2, M85Read_EX2],
+ (instregex "MVE_VMOV_q_rr")>;
+
+def : InstRW<[M85GrpABLat1Mve, M85Read_EX2],
+ (instregex "MVE_VMOV_to_lane_(8|16|32)")>;
+
+def : InstRW<[M85GrpABLat1Mve],
+ (instregex "MVE_VAND$",
+ "MVE_VBIC$", "MVE_VBICimm",
+ "MVE_VCLSs(8|16|32)",
+ "MVE_VCLZs(8|16|32)",
+ "MVE_VEOR",
+ "MVE_VMOVimmf32", "MVE_VMOVimmi(8|16|32|64)",
+ "MVE_VMVN$", "MVE_VMVNimmi(16|32)",
+ "MVE_VORN$",
+ "MVE_VORR$", "MVE_VORRimm", "MQPRCopy",
+ "MVE_VPSEL",
+ "MVE_VREV(16|32|64)_(8|16|32)"
+ )>;
+
+def : InstRW<[M85GrpABLat2MveR, M85Lat2MveR],
+ (instregex "MVE_VMOV_rr_q")>;
+
+def : InstRW<[M85GrpABLat2MveR],
+ (instregex "MVE_VMOV_from_lane_(32|u8|s8|u16|s16)")>;
+
+def : InstRW<[M85GrpALat1Mve, M85Lat1MveR,
+ M85Read_EX1, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VADC$")>;
+
+def : InstRW<[M85GrpALat1Mve, M85Lat1MveR],
+ (instregex "MVE_VADCI")>;
+
+def : InstRW<[M85GrpALat1Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VADD_qr_i(8|16|32)",
+ "MVE_VBRSR(16|32|8)",
+ "MVE_VHADD_qr_[su](8|16|32)",
+ "MVE_VHSUB_qr_[su](8|16|32)",
+ "MVE_VQADD_qr_[su](8|16|32)",
+ "MVE_VQSUB_qr_[su](8|16|32)",
+ "MVE_VSHL_qr[su](8|16|32)",
+ "MVE_VSUB_qr_i(8|16|32)"
+ )>;
+
+def : InstRW<[M85GrpALat1Mve],
+ (instregex "MVE_VABD(s|u)(8|16|32)",
+ "MVE_VABS(s|u)(8|16|32)",
+ "MVE_V(MAX|MIN)A?[us](8|16|32)",
+ "MVE_VADDi(8|16|32)",
+ "MVE_VCADDi(8|16|32)",
+ "MVE_VHCADDs(8|16|32)",
+ "MVE_VHSUB[su](8|16|32)",
+ "MVE_VMOVL[su](8|16)[tb]h",
+ "MVE_VMOVNi(16|32)[tb]h",
+ "MVE_VMULL[BT]?[p](8|16|32)(bh|th)?",
+ "MVE_VNEGs(8|16|32)",
+ "MVE_VQABSs(8|16|32)",
+ "MVE_VQADD[su](8|16|32)",
+ "MVE_VQNEGs(8|16|32)",
+ "MVE_VQSUB[su](8|16|32)",
+ "MVE_VR?HADD[su](8|16|32)",
+ "MVE_VSBC$", "MVE_VSBCI",
+ "MVE_VSHL_by_vec[su](8|16|32)",
+ "MVE_VSHL_immi(8|16|32)",
+ "MVE_VSHLL_imm[su](8|16)[bt]h",
+ "MVE_VSHLL_lw[su](8|16)[bt]h",
+ "MVE_VSHRNi(16|32)[bt]h",
+ "MVE_VSHR_imm[su](8|16|32)",
+ "MVE_VSLIimm[su]?(8|16|32)",
+ "MVE_VSRIimm[su]?(8|16|32)",
+ "MVE_VSUBi(8|16|32)"
+ )>;
+
+def : InstRW<[M85GrpALat2Mve, M85Lat2MveR, M85Read_EX2, M85Read_EX2],
+ (instregex "MVE_V(D|I)WDUPu(8|16|32)")>;
+
+def : InstRW<[M85GrpALat2Mve, M85Lat2MveR, M85Read_EX2],
+ (instregex "MVE_V(D|I)DUPu(8|16|32)")>;
+
+def : InstRW<[M85GrpALat2Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_V(Q|R|QR)SHL_qr[su](8|16|32)",
+ "MVE_VADD_qr_f(16|32)",
+ "MVE_VSUB_qr_f(16|32)"
+ )>;
+
+def : InstRW<[M85GrpALat1Mve, M85Read_EX2],
+ (instregex "MVE_VDUP(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat1Mve],
+ (instregex "MVE_VABSf(16|32)",
+ "MVE_V(MAX|MIN)NMA?f(16|32)",
+ "MVE_VNEGf(16|32)"
+ )>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Lat2MveR, M85Read_EX3, M85Read_EX3],
+ (instregex "MVE_VADDLV[us]32acc")>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Lat2MveR],
+ (instregex "MVE_VADDLV[us]32no_acc")>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Read_EX3],
+ (instregex "MVE_VADDV[us](8|16|32)acc"
+ )>;
+
+def : InstRW<[M85GrpALat2MveR, M85Read_EX3],
+ (instregex "MVE_V(MAX|MIN)A?V[us](8|16|32)",
+ "MVE_VABAV(s|u)(8|16|32)"
+ )>;
+
+def : InstRW<[M85GrpALat2MveR],
+ (instregex "MVE_VADDV[us](8|16|32)no_acc")>;
+
+def : InstRW<[M85GrpALat2Mve],
+ (instregex "MVE_V(Q|R|QR)SHL_by_vec[su](8|16|32)",
+ "MVE_VABDf(16|32)",
+ "MVE_VADDf(16|32)",
+ "MVE_VCADDf(16|32)",
+ "MVE_VQMOVU?N[su](8|16|32)[tb]h",
+ "MVE_VQR?SHL(U_)?imm[su](8|16|32)",
+ "MVE_VQR?SHRN[bt]h[su](16|32)",
+ "MVE_VQR?SHRUNs(16|32)[bt]h",
+ "MVE_VRSHR_imm[su](8|16|32)",
+ "MVE_VRSHRNi(16|32)[bt]h",
+ "MVE_VSUBf(16|32)"
+ )>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Read_EX2],
+ (instregex "MVE_V(MAX|MIN)NMA?Vf(16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VMUL_qr_i(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VQDMULL_qr_s(16|32)[tb]h")>;
+
+def : InstRW<[M85GrpBLat2Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VQR?DMULH_qr_s(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve, M85Read_EX1, M85Read_EX1, M85Read_EX3],
+ // limited accumulate bypass
+ (instregex "MVE_VMLAS?_qr_i(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve, M85Read_EX1, M85Read_EX1, M85Read_EX2],
+ // limited accumulate bypass
+ (instregex "MVE_VQR?DMLAS?H_qrs(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve],
+ // limited accumulate bypass
+ (instregex "MVE_VQR?DML[AS]DHX?s(8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Lat2MveR, M85Read_EX3, M85Read_EX3],
+ (instregex "MVE_VR?ML[AS]LDAVH?ax?[su](8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Lat2MveR],
+ (instregex "MVE_VR?ML[AS]LDAVH?x?[su](8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2MveR, M85Read_EX3],
+ (instregex "MVE_VML[AS]DAVax?[su](8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2MveR],
+ (instregex "MVE_VML[AS]DAVx?[su](8|16|32)")>;
+
+def : InstRW<[M85GrpBLat2Mve],
+ (instregex "MVE_VCVTf16(u|s)16", "MVE_VCVTf32(u|s)32",
+ "MVE_VCVT(u|s)16f16", "MVE_VCVT(u|s)32f32",
+ "MVE_VCVTf16f32", "MVE_VCVTf32f16",
+ "MVE_VMULL[BT]?[su](8|16|32)(bh|th)?",
+ "MVE_VMUL(t1)*i(8|16|32)",
+ "MVE_VQDMULLs(16|32)[tb]h",
+ "MVE_VQR?DMULHi(8|16|32)",
+ "MVE_VR?MULH[su](8|16|32)",
+ "MVE_VRINTf(16|32)"
+ )>;
+
+def : InstRW<[M85GrpBLat3Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VMUL_qr_f(16|32)")>;
+
+def : InstRW<[M85GrpBLat3Mve],
+ (instregex "MVE_VCMULf(16|32)",
+ "MVE_VMULf(16|32)"
+ )>;
+
+def : InstRW<[M85GrpBLat4Mve, M85Read_EX3, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VFMA_qr_Sf(16|32)", // VFMAS
+ "MVE_VFMA_qr_f(16|32)" // VFMA
+ )>;
+
+def : InstRW<[M85GrpBLat4Mve, M85Read_EX3],
+ (instregex "MVE_VCMLAf(16|32)")>;
+
+def : InstRW<[M85GrpBLat4Mve, M85Read_EX3],
+ (instregex "MVE_VFM(A|S)f(16|32)")>;
+
+def : InstRW<[M85GrpCLat1Mve, M85Read_EX1, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VPTv(4|8)f(16|32)r")>;
+
+def : InstRW<[M85GrpCLat1Mve, M85Read_EX1, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VPTv(4|8|16)(i|s|u)(8|16|32)r")>;
+
+def : InstRW<[M85GrpCLat1Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VCMP[isu](8|16|32)r$", "MVE_VCMPf(16|32)r$")>;
+
+def : InstRW<[M85GrpDLat1Mve, M85Read_EX2],
+ (instregex "MVE_VCTP(8|16|32|64)")>;
+
+def : InstRW<[M85GrpCLat1Mve],
+ (instregex "MVE_VCMPf(16|32)$", "MVE_VCMP[isu](8|16|32)$",
+ "MVE_VPTv(4|8)f(16|32)$",
+ "MVE_VPTv(4|8|16)(i|s|u)(8|16|32)$"
+ )>;
+
+def : InstRW<[M85GrpDLat1Mve],
+ (instregex "MVE_VPNOT",
+ "MVE_VPST"
+ )>;
+
+def : InstRW<[M85Lat2MveR, M85GrpALat2Mve, M85Read_EX1, M85Read_EX2],
+ (instregex "MVE_VSHLC")>;
+
+// VFP instructions
+
+def : WriteRes<WriteVLD1, []>;
+def : WriteRes<WriteVLD2, []>;
+def : WriteRes<WriteVLD3, []>;
+def : WriteRes<WriteVLD4, []>;
+def : WriteRes<WriteVST1, []>;
+def : WriteRes<WriteVST2, []>;
+def : WriteRes<WriteVST3, []>;
+def : WriteRes<WriteVST4, []>;
+
+} // SchedModel = CortexCortexM85Model
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-fp.s b/llvm/test/tools/llvm-mca/ARM/m85-fp.s
new file mode 100644
index 00000000000000..edc46060fe0f39
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m85-fp.s
@@ -0,0 +1,607 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+fp64,+fp16 -instruction-tables < %s | FileCheck %s
+
+vabs.f16 s0, s2
+vabs.f32 s0, s2
+vabs.f64 d0, d2
+vadd.f16 s0, s2, s1
+vadd.f32 s0, s2, s1
+vadd.f64 d0, d2, d1
+vcmp.f16 s1, s2
+vcmp.f32 s1, s2
+vcmp.f64 d1, d2
+vcmp.f16 s1, #0.0
+vcmp.f32 s1, #0.0
+vcmp.f64 d1, #0.0
+vcmpe.f16 s1, s2
+vcmpe.f32 s1, s2
+vcmpe.f64 d1, d2
+vcmpe.f16 s1, #0.0
+vcmpe.f32 s1, #0.0
+vcmpe.f64 d1, #0.0
+vcvt.f32.f64 s1, d2
+vcvt.f64.f32 d1, s1
+vcvt.f16.u16 s1, s2, #8
+vcvt.f16.s16 s1, s2, #8
+vcvt.f16.u32 s1, s2, #8
+vcvt.f16.s32 s1, s2, #8
+vcvt.u16.f16 s1, s2, #8
+vcvt.s16.f16 s1, s2, #8
+vcvt.u32.f16 s1, s2, #8
+vcvt.s32.f16 s1, s2, #8
+vcvt.f32.u16 s1, s2, #8
+vcvt.f32.s16 s1, s2, #8
+vcvt.f32.u32 s1, s2, #8
+vcvt.f32.s32 s1, s2, #8
+vcvt.u16.f32 s1, s2, #8
+vcvt.s16.f32 s1, s2, #8
+vcvt.u32.f32 s1, s2, #8
+vcvt.s32.f32 s1, s2, #8
+vcvt.f64.u16 d1, d2, #8
+vcvt.f64.s16 d1, d2, #8
+vcvt.f64.u32 d1, d2, #8
+vcvt.f64.s32 d1, d2, #8
+vcvt.u16.f64 d1, d2, #8
+vcvt.s16.f64 d1, d2, #8
+vcvt.u32.f64 d1, d2, #8
+vcvt.s32.f64 d1, d2, #8
+vcvt.u32.f16 s1, s2
+vcvt.s32.f16 s1, s2
+vcvt.u32.f32 s1, s2
+vcvt.s32.f32 s1, s2
+vcvt.u32.f64 s1, d2
+vcvt.s32.f64 s1, d2
+vcvt.f16.u32 s1, s2
+vcvt.f16.s32 s1, s2
+vcvt.f32.u32 s1, s2
+vcvt.f32.s32 s1, s2
+vcvt.f64.u32 d1, s2
+vcvt.f64.s32 d1, s2
+vcvta.u32.f16 s1, s2
+vcvta.s32.f16 s1, s2
+vcvta.u32.f32 s1, s2
+vcvta.s32.f32 s1, s2
+vcvta.u32.f64 s1, d2
+vcvta.s32.f64 s1, d2
+vcvtm.u32.f16 s1, s2
+vcvtm.s32.f16 s1, s2
+vcvtm.u32.f32 s1, s2
+vcvtm.s32.f32 s1, s2
+vcvtm.u32.f64 s1, d2
+vcvtm.s32.f64 s1, d2
+vcvtn.u32.f16 s1, s2
+vcvtn.s32.f16 s1, s2
+vcvtn.u32.f32 s1, s2
+vcvtn.s32.f32 s1, s2
+vcvtn.u32.f64 s1, d2
+vcvtn.s32.f64 s1, d2
+vcvtp.u32.f16 s1, s2
+vcvtp.s32.f16 s1, s2
+vcvtp.u32.f32 s1, s2
+vcvtp.s32.f32 s1, s2
+vcvtp.u32.f64 s1, d2
+vcvtp.s32.f64 s1, d2
+vcvtb.f16.f32 s1, s2
+vcvtb.f16.f64 s1, d2
+vcvtb.f32.f16 s1, s2
+vcvtb.f64.f16 d1, s2
+vcvtr.u32.f16 s1, s2
+vcvtr.s32.f16 s1, s2
+vcvtr.u32.f32 s1, s2
+vcvtr.s32.f32 s1, s2
+vcvtr.u32.f64 s1, d2
+vcvtr.s32.f64 s1, d2
+vcvtt.f16.f32 s1, s2
+vcvtt.f16.f64 s1, d2
+vcvtt.f32.f16 s1, s2
+vcvtt.f64.f16 d1, s2
+vdiv.f16 s0, s2, s1
+vdiv.f32 s0, s2, s1
+vdiv.f64 d0, d2, d1
+vfma.f16 s0, s2, s1
+vfma.f32 s0, s2, s1
+vfma.f64 d0, d2, d1
+vfms.f16 s0, s2, s1
+vfms.f32 s0, s2, s1
+vfms.f64 d0, d2, d1
+vfnma.f16 s0, s2, s1
+vfnma.f32 s0, s2, s1
+vfnma.f64 d0, d2, d1
+vfnms.f16 s0, s2, s1
+vfnms.f32 s0, s2, s1
+vfnms.f64 d0, d2, d1
+vins.f16 s0, s1
+vmaxnm.f16 s0, s2, s1
+vmaxnm.f32 s0, s2, s1
+vmaxnm.f64 d0, d2, d1
+vminnm.f16 s0, s2, s1
+vminnm.f32 s0, s2, s1
+vminnm.f64 d0, d2, d1
+vmla.f16 s0, s2, s1
+vmla.f32 s0, s2, s1
+vmla.f64 d0, d2, d1
+vmls.f16 s0, s2, s1
+vmls.f32 s0, s2, s1
+vmls.f64 d0, d2, d1
+vmov.f16 s0, r1
+vmov.f16 r0, s1
+vmov.f32 s0, r1
+vmov.f32 r0, s1
+vmov.f64 d0, r1, r2
+vmov.f64 r0, r1, d1
+vmov s0, s1, r0, r1
+vmov r0, r1, s0, s1
+vmov.f16 s0, #1.0
+vmov.f32 s0, #1.0
+vmov.f64 d0, #1.0
+vmov.f32 s0, s1
+vmov.f64 d0, d1
+vmovx.f16 s0, s1
+vmul.f16 s0, s2, s1
+vmul.f32 s0, s2, s1
+vmul.f64 d0, d2, d1
+vneg.f16 s0, s2
+vneg.f32 s0, s2
+vneg.f64 d0, d2
+vnmla.f16 s0, s2, s1
+vnmla.f32 s0, s2, s1
+vnmla.f64 d0, d2, d1
+vnmls.f16 s0, s2, s1
+vnmls.f32 s0, s2, s1
+vnmls.f64 d0, d2, d1
+vnmul.f16 s0, s2, s1
+vnmul.f32 s0, s2, s1
+vnmul.f64 d0, d2, d1
+vrinta.f16 s0, s2
+vrinta.f32.f32 s0, s2
+vrinta.f64.f64 d0, d2
+vrintm.f16 s0, s2
+vrintm.f32.f32 s0, s2
+vrintm.f64.f64 d0, d2
+vrintn.f16 s0, s2
+vrintn.f32.f32 s0, s2
+vrintn.f64.f64 d0, d2
+vrintp.f16 s0, s2
+vrintp.f32.f32 s0, s2
+vrintp.f64.f64 d0, d2
+vrintr.f16.f16 s0, s2
+vrintr.f32.f32 s0, s2
+vrintr.f64.f64 d0, d2
+vrintz.f16.f16 s0, s2
+vrintz.f32.f32 s0, s2
+vrintz.f64.f64 d0, d2
+vrintx.f16.f16 s0, s2
+vrintx.f32.f32 s0, s2
+vrintx.f64.f64 d0, d2
+vseleq.f16 s0, s2, s1
+vseleq.f32 s0, s2, s1
+vseleq.f64 d0, d2, d1
+vsqrt.f16 s0, s2
+vsqrt.f32 s0, s2
+vsqrt.f64 d0, d2
+vsub.f16 s0, s2, s1
+vsub.f32 s0, s2, s1
+vsub.f64 d0, d2, d1
+
+vldr.f64 d0, [r0]
+vldr.f32 s0, [r0]
+vldr.16 s0, [r0]
+vstr.f64 d0, [r0]
+vstr.f32 s0, [r0]
+vstr.16 s0, [r0]
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 vabs.f16 s0, s2
+# CHECK-NEXT: 1 1 1.00 vabs.f32 s0, s2
+# CHECK-NEXT: 1 1 1.00 vabs.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vadd.f16 s0, s2, s1
+# CHECK-NEXT: 1 2 1.00 vadd.f32 s0, s2, s1
+# CHECK-NEXT: 1 6 1.00 vadd.f64 d0, d2, d1
+# CHECK-NEXT: 1 1 1.00 vcmp.f16 s1, s2
+# CHECK-NEXT: 1 1 1.00 vcmp.f32 s1, s2
+# CHECK-NEXT: 1 1 1.00 vcmp.f64 d1, d2
+# CHECK-NEXT: 1 1 1.00 vcmp.f16 s1, #0
+# CHECK-NEXT: 1 1 1.00 vcmp.f32 s1, #0
+# CHECK-NEXT: 1 1 1.00 vcmp.f64 d1, #0
+# CHECK-NEXT: 1 1 1.00 vcmpe.f16 s1, s2
+# CHECK-NEXT: 1 1 1.00 vcmpe.f32 s1, s2
+# CHECK-NEXT: 1 1 1.00 vcmpe.f64 d1, d2
+# CHECK-NEXT: 1 1 1.00 vcmpe.f16 s1, #0
+# CHECK-NEXT: 1 1 1.00 vcmpe.f32 s1, #0
+# CHECK-NEXT: 1 1 1.00 vcmpe.f64 d1, #0
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.f32 d1, s1
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.u16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.s16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.u32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.s32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u16.f16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s16.f16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.u16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.s16 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.u32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.s32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u16.f32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s16.f32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f32 s1, s1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.u16 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.s16 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.u32 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.s32 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u16.f64 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s16.f64 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f64 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f64 d1, d1, #8
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvt.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.u32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.f16.s32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.u32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.f32.s32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.u32 d1, s2
+# CHECK-NEXT: 1 2 1.00 vcvt.f64.s32 d1, s2
+# CHECK-NEXT: 1 2 1.00 vcvta.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvta.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvta.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvta.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvta.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvta.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtm.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtm.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtm.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtm.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtm.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtm.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtn.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtn.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtn.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtn.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtn.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtn.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtp.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtp.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtp.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtp.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtp.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtp.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtb.f16.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtb.f16.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtb.f32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtb.f64.f16 d1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtr.u32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtr.s32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtr.u32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtr.s32.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtr.u32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtr.s32.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtt.f16.f32 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtt.f16.f64 s1, d2
+# CHECK-NEXT: 1 2 1.00 vcvtt.f32.f16 s1, s2
+# CHECK-NEXT: 1 2 1.00 vcvtt.f64.f16 d1, s2
+# CHECK-NEXT: 1 8 1.00 vdiv.f16 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vdiv.f32 s0, s2, s1
+# CHECK-NEXT: 1 29 1.00 vdiv.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vfma.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vfma.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vfma.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vfms.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vfms.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vfms.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vfnma.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vfnma.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vfnma.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vfnms.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vfnms.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vfnms.f64 d0, d2, d1
+# CHECK-NEXT: 1 1 1.00 vins.f16 s0, s1
+# CHECK-NEXT: 1 1 1.00 vmaxnm.f16 s0, s2, s1
+# CHECK-NEXT: 1 1 1.00 vmaxnm.f32 s0, s2, s1
+# CHECK-NEXT: 1 1 1.00 vmaxnm.f64 d0, d2, d1
+# CHECK-NEXT: 1 1 1.00 vminnm.f16 s0, s2, s1
+# CHECK-NEXT: 1 1 1.00 vminnm.f32 s0, s2, s1
+# CHECK-NEXT: 1 1 1.00 vminnm.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vmla.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vmla.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vmla.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vmls.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vmls.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vmls.f64 d0, d2, d1
+# CHECK-NEXT: 1 1 1.00 vmov.f16 s0, r1
+# CHECK-NEXT: 1 2 1.00 vmov.f16 r0, s1
+# CHECK-NEXT: 1 1 1.00 vmov s0, r1
+# CHECK-NEXT: 1 2 1.00 vmov r0, s1
+# CHECK-NEXT: 1 1 1.00 vmov d0, r1, r2
+# CHECK-NEXT: 1 2 1.00 vmov r0, r1, d1
+# CHECK-NEXT: 1 1 1.00 vmov s0, s1, r0, r1
+# CHECK-NEXT: 1 2 1.00 vmov r0, r1, s0, s1
+# CHECK-NEXT: 1 1 1.00 vmov.f16 s0, #1.000000e+00
+# CHECK-NEXT: 1 1 1.00 vmov.f32 s0, #1.000000e+00
+# CHECK-NEXT: 1 1 1.00 vmov.f64 d0, #1.000000e+00
+# CHECK-NEXT: 1 1 1.00 vmov.f32 s0, s1
+# CHECK-NEXT: 1 1 1.00 vmov.f64 d0, d1
+# CHECK-NEXT: 1 1 1.00 vmovx.f16 s0, s1
+# CHECK-NEXT: 1 3 1.00 vmul.f16 s0, s2, s1
+# CHECK-NEXT: 1 3 1.00 vmul.f32 s0, s2, s1
+# CHECK-NEXT: 1 8 1.00 vmul.f64 d0, d2, d1
+# CHECK-NEXT: 1 1 1.00 vneg.f16 s0, s2
+# CHECK-NEXT: 1 1 1.00 vneg.f32 s0, s2
+# CHECK-NEXT: 1 1 1.00 vneg.f64 d0, d2
+# CHECK-NEXT: 1 5 1.00 vnmla.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vnmla.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vnmla.f64 d0, d2, d1
+# CHECK-NEXT: 1 5 1.00 vnmls.f16 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vnmls.f32 s0, s2, s1
+# CHECK-NEXT: 1 14 1.00 vnmls.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vnmul.f16 s0, s2, s1
+# CHECK-NEXT: 1 3 1.00 vnmul.f32 s0, s2, s1
+# CHECK-NEXT: 1 8 1.00 vnmul.f64 d0, d2, d1
+# CHECK-NEXT: 1 2 1.00 vrinta.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrinta.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrinta.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintm.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintm.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintm.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintn.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintn.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintn.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintp.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintp.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintp.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintr.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintr.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintr.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintz.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintz.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintz.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vrintx.f16 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintx.f32 s0, s2
+# CHECK-NEXT: 1 2 1.00 vrintx.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vseleq.f16 s0, s2, s1
+# CHECK-NEXT: 1 2 1.00 vseleq.f32 s0, s2, s1
+# CHECK-NEXT: 1 2 1.00 vseleq.f64 d0, d2, d1
+# CHECK-NEXT: 1 8 1.00 vsqrt.f16 s0, s2
+# CHECK-NEXT: 1 14 1.00 vsqrt.f32 s0, s2
+# CHECK-NEXT: 1 29 1.00 vsqrt.f64 d0, d2
+# CHECK-NEXT: 1 2 1.00 vsub.f16 s0, s2, s1
+# CHECK-NEXT: 1 2 1.00 vsub.f32 s0, s2, s1
+# CHECK-NEXT: 1 6 1.00 vsub.f64 d0, d2, d1
+# CHECK-NEXT: 1 2 1.00 * vldr d0, [r0]
+# CHECK-NEXT: 1 2 0.50 * vldr s0, [r0]
+# CHECK-NEXT: 1 2 0.50 * vldr.16 s0, [r0]
+# CHECK-NEXT: 1 2 1.00 * vstr d0, [r0]
+# CHECK-NEXT: 1 2 0.50 * vstr s0, [r0]
+# CHECK-NEXT: 1 2 0.50 * vstr.16 s0, [r0]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M85UnitALU
+# CHECK-NEXT: [0.1] - M85UnitALU
+# CHECK-NEXT: [1] - M85UnitBranch
+# CHECK-NEXT: [2] - M85UnitDiv
+# CHECK-NEXT: [3] - M85UnitLShift
+# CHECK-NEXT: [4] - M85UnitLoadH
+# CHECK-NEXT: [5] - M85UnitLoadL
+# CHECK-NEXT: [6] - M85UnitMAC
+# CHECK-NEXT: [7] - M85UnitSIMD
+# CHECK-NEXT: [8] - M85UnitShift1
+# CHECK-NEXT: [9] - M85UnitShift2
+# CHECK-NEXT: [10] - M85UnitSlot0
+# CHECK-NEXT: [11] - M85UnitStoreH
+# CHECK-NEXT: [12] - M85UnitStoreL
+# CHECK-NEXT: [13] - M85UnitVFPAH
+# CHECK-NEXT: [14] - M85UnitVFPAL
+# CHECK-NEXT: [15] - M85UnitVFPBH
+# CHECK-NEXT: [16] - M85UnitVFPBL
+# CHECK-NEXT: [17] - M85UnitVFPCH
+# CHECK-NEXT: [18] - M85UnitVFPCL
+# CHECK-NEXT: [19] - M85UnitVFPD
+# CHECK-NEXT: [20] - M85UnitVPortH
+# CHECK-NEXT: [21] - M85UnitVPortL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
+# CHECK-NEXT: - - - - - 2.00 2.00 - - - - 181.00 2.00 2.00 8.00 8.00 96.00 96.00 8.00 8.00 - 126.50 126.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vabs.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vabs.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vabs.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vadd.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vadd.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 1.00 1.00 - - - - - 1.00 1.00 vadd.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmp.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmp.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 1.00 1.00 - 1.00 1.00 vcmp.f64 d1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmp.f16 s1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmp.f32 s1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 1.00 1.00 - 1.00 1.00 vcmp.f64 d1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmpe.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmpe.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 1.00 1.00 - 1.00 1.00 vcmpe.f64 d1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmpe.f16 s1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 0.50 0.50 - 0.50 0.50 vcmpe.f32 s1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 1.00 1.00 - 1.00 1.00 vcmpe.f64 d1, #0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.f32 d1, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.u16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.s16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.u32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.s32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u16.f16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s16.f16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u32.f16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s32.f16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.u16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.s16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.u32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.s32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u16.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s16.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u32.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s32.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.u16 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.s16 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.u32 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.s32 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.u16.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.s16.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.u32.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.s32.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.u32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f16.s32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.u32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvt.f32.s32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.u32 d1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvt.f64.s32 d1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvta.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvta.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvta.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvta.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvta.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvta.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtm.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtm.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtm.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtm.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtm.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtm.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtn.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtn.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtn.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtn.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtn.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtn.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtp.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtp.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtp.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtp.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtp.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtp.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtb.f16.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtb.f16.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtb.f32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtb.f64.f16 d1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtr.u32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtr.s32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtr.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtr.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtr.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtr.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtt.f16.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtt.f16.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vcvtt.f32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vcvtt.f64.f16 d1, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vdiv.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vdiv.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vdiv.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfma.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfma.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vfma.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfms.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfms.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vfms.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfnma.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfnma.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vfnma.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfnms.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vfnms.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vfnms.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vins.f16 s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vmaxnm.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vmaxnm.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 1.00 1.00 - - - - - 1.00 1.00 vmaxnm.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vminnm.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vminnm.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 1.00 1.00 - - - - - 1.00 1.00 vminnm.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmla.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmla.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vmla.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmls.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmls.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vmls.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov.f16 s0, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov.f16 r0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov s0, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov r0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov d0, r1, r2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov r0, r1, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov s0, s1, r0, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov r0, r1, s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov.f16 s0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov.f32 s0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.f64 d0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmov.f32 s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.f64 d0, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 0.50 0.50 vmovx.f16 s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmul.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vmul.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vmul.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vneg.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vneg.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vneg.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmla.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmla.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vnmla.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmls.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmls.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vnmls.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmul.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vnmul.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vnmul.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrinta.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrinta.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrinta.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintm.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintm.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintm.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintn.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintn.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintn.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintp.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintp.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintp.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintr.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintr.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintr.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintz.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintz.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintz.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintx.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vrintx.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vrintx.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vseleq.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vseleq.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vseleq.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vsqrt.f16 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 0.50 0.50 - - - 0.50 0.50 vsqrt.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 1.00 1.00 - - - 1.00 1.00 vsqrt.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vsub.f16 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 0.50 0.50 - - - - - 0.50 0.50 vsub.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 1.00 1.00 - - - - - 1.00 1.00 vsub.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - 1.00 1.00 vldr d0, [r0]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - 0.50 0.50 vldr s0, [r0]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - 0.50 0.50 vldr.16 s0, [r0]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - 1.00 1.00 vstr d0, [r0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - 0.50 0.50 vstr s0, [r0]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - 0.50 0.50 vstr.16 s0, [r0]
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-int.s b/llvm/test/tools/llvm-mca/ARM/m85-int.s
new file mode 100644
index 00000000000000..ae6570e1048637
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m85-int.s
@@ -0,0 +1,1505 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s
+
+adc r0, r1, #0
+adcs r0, r1, #0
+adcs r0, r1
+adc.w r0, r1, r2
+adcs.w r0, r1, r2
+adc.w r0, r1, r2, LSL #1
+adcs.w r0, r1, r2, LSL #1
+add r0, sp, #1
+add sp, #1
+add.w r0, sp, #1
+adds.w r0, sp, #1
+addw r0, sp, #1
+add r0, sp, r0
+add sp, r1
+add.w r0, sp, r1
+adds.w r0, sp, r1
+add.w r0, sp, r1, LSL #1
+adds.w r0, sp, r1, LSL #1
+adds r0, r1, #1
+adds r0, #42
+add.w r0, r1, #1
+adds.w r0, r1, #1
+addw r0, r1, #1
+adds r0, r1, r2
+add r0, r1
+add.w r0, r1, r2
+adds.w r0, r1, r2
+add.w r0, r1, r2, LSL #1
+adds.w r0, r1, r2, LSL #1
+adr r0, #-6
+adr r8, #-6
+adr.w r0, #-6
+and r0, r1, #1
+ands r0, r1, #1
+ands r1, r0
+and.w r0, r1, r2
+ands.w r0, r1, r2
+and.w r0, r1, r2, LSL #1
+ands.w r0, r1, r2, LSL #1
+asrs r0, r1, #1
+asr.w r0, r1, #1
+asrs.w r0, r1, #1
+asrs r0, r1
+asr.w r0, r1, r2
+asrs.w r0, r1, r2
+asrl r0, r1, #1
+asrl r0, r1, r2
+bfc r0, #1, #2
+bfi r0, r1, #1, #2
+bic r0, r1, #1
+bics r0, r1, #1
+bics r0, r1
+bic.w r0, r1, r2
+bics.w r0, r1, r2
+bic.w r0, r1, r2, LSL #1
+bics.w r0, r1, r2, LSL #1
+bkpt #1
+clrex
+clrm {r1, r2}
+clz r0, r1
+cmn r0, #1
+cmn r0, r1
+cmn.w r0, r1
+cmn.w r0, r1, LSL #1
+cmp r0, #1
+cmp.w r0, #1
+cmp r0, r1
+cmp r0, r10
+cmp.w r0, r1
+cmp.w r0, r1, LSL #1
+#cpsdb 1
+#cpsie if
+csdb
+csel r1, r2, r3, eq
+csinc r1, r2, r3, eq
+csinv r1, r2, r3, eq
+csneg r1, r2, r3, eq
+#dbg #1
+dmb
+dsb
+eor r0, r1, #1
+eors r0, r1, #1
+eors r0, r1
+eor.w r0, r1, r2
+eors.w r0, r1, r2
+eor.w r0, r1, r2, LSL #1
+eors.w r0, r1, r2, LSL #1
+esb
+isb
+lctp
+lda r0, [r1]
+ldab r0, [r1]
+ldaex r0, [r1]
+ldaexb r0, [r1]
+ldaexh r0, [r1]
+ldah r0, [r1]
+ldm r0!, {r1}
+ldm r0, {r1}
+ldm.w r0, {r1}
+ldm.w r0!, {r1}
+ldmdb r0, {r1}
+ldmdb r0!, {r1}
+ldr r0, [r1, #4]
+ldr r0, [sp, #4]
+ldr.w r0, [r1, #4]
+ldr r0, [r1, #-1]
+ldr r0, [r1], #1
+ldr r0, [r1, #1]!
+ldr r0, #4
+ldr.w r0, #4
+ldr r0, next
+ldr.w r0, next
+ldr r0, [r1, r2]
+ldr.w r0, [r1, r2]
+ldr.w r0, [r1, r2, LSL #1]
+ldrb r0, [r1, #1]
+ldrb.w r0, [r1, #1]
+ldrb r0, [r1, #-1]
+ldrb r0, [r1], #1
+ldrb r0, [r1, #1]!
+ldrb r0, #4
+ldrb r0, next
+ldrb r0, [r1, r2]
+ldrb.w r0, [r1, r2]
+ldrb.w r0, [r1, r2, LSL #1]
+ldrbt r0, [r1, #1]
+ldrd r0, r2, [r1]
+ldrd r0, r2, [r1, #-4]
+ldrd r0, r2, [r1], #4
+ldrd r0, r2, [r1, #4]!
+ldrd r0, r2, next
+next:
+ldrex r0, [r1]
+ldrex r0, [r1, #4]
+ldrexb r0, [r1]
+ldrexh r0, [r1]
+ldrh r0, [r1, #2]
+ldrh.w r0, [r1, #1]
+ldrh r0, [r1, #-1]
+ldrh r0, [r1], #1
+ldrh r0, [r1, #1]!
+ldrh r0, #4
+ldrh r0, next
+ldrh r0, [r1, r2]
+ldrh.w r0, [r1, r2]
+ldrh.w r0, [r1, r2, LSL #1]
+ldrht r0, [r1, #1]
+ldrsb r0, [r1, #1]
+ldrsb r0, [r1, #-1]
+ldrsb r0, [r1], #1
+ldrsb r0, [r1, #1]!
+ldrsb r0, #4
+ldrsb r0, next
+ldrsb r0, [r1, r2]
+ldrsb.w r0, [r1, r2]
+ldrsb.w r0, [r1, r2, LSL #1]
+ldrsbt r0, [r1, #1]
+ldrsh r0, [r1, #2]
+ldrsh r0, [r1, #-1]
+ldrsh r0, [r1], #1
+ldrsh r0, [r1, #1]!
+ldrsh r0, #4
+ldrsh r0, next
+ldrsh r0, [r1, r2]
+ldrsh.w r0, [r1, r2]
+ldrsh.w r0, [r1, r2, LSL #1]
+ldrsht r0, [r1, #1]
+ldrt r0, [r1, #1]
+le lr, next
+le next
+letp lr, next
+lsls r0, r1, #1
+lsl.w r0, r1, #1
+lsls.w r0, r1, #1
+lsls r0, r1
+lsl.w r0, r1, r2
+lsls.w r0, r1, r2
+lsll r0, r1, #2
+lsll r0, r1, r2
+lsrs r0, r1, #1
+lsr.w r0, r1, #1
+lsrs.w r0, r1, #1
+lsrs r0, r1
+lsr.w r0, r1, r2
+lsrs.w r0, r1, r2
+lsrl r0, r1, #2
+mla r0, r1, r2, r3
+mls r0, r1, r2, r3
+movs r0, #1
+mov.w r0, #1
+movs.w r0, #1
+movw r0, #1
+mov r0, r1
+#movs r0, r1
+mov.w r0, r1
+movs.w r0, r1
+movt r0, #1
+mrs r0, apsr
+msr apsr, r0
+muls r1, r2, r1
+mul r0, r1, r2
+mvn r0, #1
+mvns r0, #1
+mvns r0, r1
+mvn.w r0, r1
+mvns.w r0, r1
+mvn.w r0, r1, LSL #1
+mvns.w r0, r1, LSL #1
+nop
+nop.w
+orn r0, r1, #1
+orns r0, r1, #1
+orn r0, r1, r2
+orns r0, r1, r2
+orn r0, r1, r2, LSL #1
+orns r0, r1, r2, LSL #1
+orr r0, r1, #1
+orrs r0, r1, #1
+orrs r0, r1
+orr r0, r1, r2
+orrs r0, r1, r2
+orr r0, r1, r2, LSL #1
+orrs r0, r1, r2, LSL #1
+pkhbt r0, r1, r2
+pkhbt r0, r1, r2, LSL #1
+pkhtb r0, r1, r2
+pkhtb r0, r1, r2, ASR #1
+pop { r0 }
+pop.w { r0, r1 }
+pop.w { r0 }
+pssbb
+push { r0 }
+push.w { r0, r1 }
+push.w { r0 }
+qadd r0, r1, r2
+qadd16 r0, r1, r2
+qadd8 r0, r1, r2
+qasx r0, r1, r2
+qdadd r0, r1, r2
+qdsub r0, r1, r2
+qsax r0, r1, r2
+qsub r0, r1, r2
+qsub16 r0, r1, r2
+qsub8 r0, r1, r2
+rbit r0, r1
+rev r0, r1
+rev.w r0, r1
+rev16 r0, r1
+rev16.w r0, r1
+revsh r0, r1
+revsh.w r0, r1
+ror r0, r1, #1
+rors r0, r1, #1
+rors r0, r1
+ror.w r0, r1, r2
+rors.w r0, r1, r2
+rrx r0, r1
+rrxs r0, r1
+rsbs r0, r1, #0
+rsb.w r0, r1, #1
+rsbs.w r0, r1, #1
+rsb r0, r1, r2
+rsbs r0, r1, r2
+rsb r0, r1, r2, LSL #1
+rsbs r0, r1, r2, LSL #1
+sadd16 r0, r1, r2
+sadd8 r0, r1, r2
+sasx r0, r1, r2
+sbc r0, r1, #1
+sbcs r0, r1, #1
+sbcs r0, r1
+sbc r0, r1, r2
+sbcs r0, r1, r2
+sbc r0, r1, r2, LSL #1
+sbcs r0, r1, r2, LSL #1
+sbfx r0, r1, #1, #2
+sdiv r0, r1, r2
+sel r0, r1, r2
+sev
+#sg
+shadd16 r0, r1, r2
+shadd8 r0, r1, r2
+shasx r0, r1, r2
+shsax r0, r1, r2
+shsub16 r0, r1, r2
+shsub8 r0, r1, r2
+smlabb r0, r1, r2, r3
+smlabt r0, r1, r2, r3
+smlatb r0, r1, r2, r3
+smlatt r0, r1, r2, r3
+smlad r0, r1, r2, r3
+smladx r0, r1, r2, r3
+smlal r0, r1, r2, r3
+smlalbb r0, r1, r2, r3
+smlalbt r0, r1, r2, r3
+smlaltb r0, r1, r2, r3
+smlaltt r0, r1, r2, r3
+smlald r0, r1, r2, r3
+smlaldx r0, r1, r2, r3
+smlawb r0, r1, r2, r3
+smlawt r0, r1, r2, r3
+smlsd r0, r1, r2, r3
+smlsdx r0, r1, r2, r3
+smlsld r0, r1, r2, r3
+smlsldx r0, r1, r2, r3
+smmla r0, r1, r2, r3
+smmlar r0, r1, r2, r3
+smmls r0, r1, r2, r3
+smmlsr r0, r1, r2, r3
+smmul r0, r1, r2
+smmulr r0, r1, r2
+smuad r0, r1, r2
+smuadx r0, r1, r2
+smulbb r0, r1, r2
+smulbt r0, r1, r2
+smultb r0, r1, r2
+smultt r0, r1, r2
+smull r0, r1, r2, r3
+smulwb r0, r1, r2
+smulwt r0, r1, r2
+smusd r0, r1, r2
+smusdx r0, r1, r2
+sqrshr r0, r1
+sqrshrl r0, r1, #48, r2
+sqshl r0, #7
+sqshll r0, r1, #7
+srshr r0, #7
+srshrl r0, r1, #7
+ssat r0, #1, r2
+ssat r0, #1, r2, LSL #1
+ssat16 r0, #1, r1
+ssax r0, r1, r2
+ssbb
+ssub16 r0, r1, r2
+ssub8 r0, r1, r2
+stl r0, [r1]
+stlb r0, [r1]
+stlex r0, r1, [r2]
+stlexb r0, r1, [r2]
+stlexh r0, r1, [r2]
+stlh r0, [r1]
+stm r0!, { r1 }
+stm.w r0, { r1 }
+stm.w r0!, { r1 }
+stmdb r0, { r1 }
+stmdb r0!, { r1 }
+str r0, [ r1 ]
+str r0, [ r1, #4 ]
+str r0, [ sp, #4 ]
+str.w r0, [ r1, #1 ]
+str r0, [ r1, #-1 ]
+str r0, [ r1 ], #1
+#str r0, [ r1, #1 ]!
+str r0, [ r1, r2 ]
+str.w r0, [ r1, r2 ]
+str.w r0, [ r1, r2, LSL #1 ]
+strb r0, [ r1 ]
+strb r0, [ r1, #1 ]
+strb.w r0, [ r1, #1 ]
+strb r0, [ r1, #-1 ]
+strb r0, [ r1 ], #1
+strb r0, [ r1, #1 ]!
+strb r0, [ r1, r2 ]
+strb.w r0, [ r1, r2 ]
+strb.w r0, [ r1, r2, LSL #1 ]
+strbt r0, [ r1, #1 ]
+strd r0, r1, [ r2, #4 ]
+strd r0, r1, [ r2 ], #4
+strd r0, r1, [ r2, #4 ]!
+strex r0, r1, [ r2 ]
+strex r0, r1, [ r2, #4 ]
+strexb r0, r1, [ r2 ]
+strexh r0, r1, [ r2 ]
+strh r0, [ r1 ]
+strh r0, [ r1, #2 ]
+strh.w r0, [ r1, #2 ]
+strh r0, [ r1, #-1 ]
+strh r0, [ r1 ], #1
+strh r0, [ r1, #1 ]!
+strh r0, [ r1, r2 ]
+strh.w r0, [ r1, r2 ]
+strh.w r0, [ r1, r2, LSL #1 ]
+strht r0, [r1, #1 ]
+strt r0, [r1, #1 ]
+sub sp, sp, #4
+sub.w r0, sp, #1
+subs.w r0, sp, #1
+subw r0, sp, #1
+sub r0, sp, r1
+subs r0, sp, r1
+sub r0, sp, r1, LSL #1
+subs r0, sp, r1, LSL #1
+subs r0, r1, #1
+subs r0, #1
+sub.w r0, r1, #1
+subs.w r0, r1, #1
+subw r0, r1, #1
+subs r0, r1, r2
+sub.w r0, r1, r2
+subs.w r0, r1, r2
+sub.w r0, r1, r2, LSL #1
+subs.w r0, r1, r2, LSL #1
+#svc #1 ; treated as a call
+sxtab r0, r1, r2
+sxtab r0, r1, r2, ROR #8
+sxtab16 r0, r1, r2
+sxtab16 r0, r1, r2, ROR #8
+sxtah r0, r1, r2
+sxtah r0, r1, r2, ROR #8
+sxtb r0, r1
+sxtb.w r0, r1
+sxtb.w r0, r1, ROR #8
+sxtb16 r0, r1
+sxtb16 r0, r1, ROR #8
+sxth r0, r1
+sxth.w r0, r1
+sxth.w r0, r1, ROR #8
+tbb [r0, r1]
+tbh [r0, r1, LSL #1]
+teq r0, #1
+teq r0, r1
+teq r0, r1, LSL #1
+tst r0, #1
+tst r0, r1
+tst.w r0, r1
+tst.w r0, r1, LSL #1
+#tt r0, r1
+#ttt r0, r1
+#tta r0, r1
+#ttat r0, r1
+uadd16 r0, r1, r2
+uadd8 r0, r1, r2
+uasx r0, r1, r2
+ubfx r0, r1, #1, #2
+#udf #1
+udiv r0, r1, r2
+uhadd16 r0, r1, r2
+uhadd8 r0, r1, r2
+uhasx r0, r1, r2
+uhsax r0, r1, r2
+uhsub16 r0, r1, r2
+uhsub8 r0, r1, r2
+umaal r0, r1, r2, r3
+umlal r0, r1, r2, r3
+umull r0, r1, r2, r3
+uqadd16 r0, r1, r2
+uqadd8 r0, r1, r2
+uqasx r0, r1, r2
+uqrshl r0, r1
+uqrshll r0, r1, #48, r2
+uqsax r0, r1, r2
+uqshl r0, #1
+uqshll r0, r1, #1
+uqsub16 r0, r1, r2
+uqsub8 r0, r1, r2
+urshr r0, #1
+urshrl r0, r1, #1
+usad8 r0, r1, r2
+usada8 r0, r1, r2, r3
+usat r0, #1, r1
+usat r0, #1, r1, LSL #1
+usat16 r0, #1, r1
+usax r0, r1, r2
+usub16 r0, r1, r2
+usub8 r0, r1, r2
+uxtab r0, r1, r2
+uxtab r0, r1, r2, ROR #8
+uxtab16 r0, r1, r2
+uxtab16 r0, r1, r2, ROR #8
+uxtah r0, r1, r2
+uxtah r0, r1, r2, ROR #8
+uxtb r0, r1
+uxtb.w r0, r1
+uxtb.w r0, r1, ROR #8
+uxtb16 r0, r1
+uxtb16 r0, r1, ROR #8
+uxth r0, r1
+uxth.w r0, r1
+uxth.w r0, r1, ROR #8
+wfe
+wfe.w
+wfi
+wfi.w
+wls lr, r0, forward
+dls lr, r0
+wlstp.8 lr, r0, forward
+wlstp.16 lr, r0, forward
+wlstp.32 lr, r0, forward
+wlstp.64 lr, r0, forward
+dlstp.8 lr, r0
+dlstp.16 lr, r0
+dlstp.32 lr, r0
+dlstp.64 lr, r0
+forward:
+yield
+yield.w
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 adc r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 adcs r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 U adcs r0, r1
+# CHECK-NEXT: 1 2 1.00 adc.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 adcs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 adc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 adcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 U add.w sp, sp, #1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 addw r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 U add r0, sp, r0
+# CHECK-NEXT: 1 2 0.50 U add sp, r1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, r1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, sp, r1
+# CHECK-NEXT: 1 2 1.00 add.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 adds.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 adds r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds r0, #42
+# CHECK-NEXT: 1 1 0.50 add.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 addw r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 add r0, r1
+# CHECK-NEXT: 1 1 0.50 add.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 adds.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 add.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 adds.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 U adr.w r0, #-6
+# CHECK-NEXT: 1 1 0.50 U adr.w r8, #-6
+# CHECK-NEXT: 1 1 0.50 U adr.w r0, #-6
+# CHECK-NEXT: 1 1 0.50 and r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 ands r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 ands r1, r0
+# CHECK-NEXT: 1 1 0.50 and.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 ands.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 and.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 1.00 ands.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 asrs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 asr.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 asrs.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 asrs r0, r1
+# CHECK-NEXT: 1 1 0.50 asr.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 asrs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 asrl r0, r1, #1
+# CHECK-NEXT: 1 2 1.00 asrl r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 bfc r0, #1, #2
+# CHECK-NEXT: 1 1 1.00 bfi r0, r1, #1, #2
+# CHECK-NEXT: 1 1 0.50 bic r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 bics r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 bics r0, r1
+# CHECK-NEXT: 1 2 1.00 bic.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 bics.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 bic.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 bics.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 3 0.50 U bkpt #1
+# CHECK-NEXT: 1 3 0.50 * * U clrex
+# CHECK-NEXT: 1 3 0.50 U clrm {r1, r2}
+# CHECK-NEXT: 1 1 1.00 clz r0, r1
+# CHECK-NEXT: 1 1 0.50 cmn.w r0, #1
+# CHECK-NEXT: 1 1 0.50 cmn r0, r1
+# CHECK-NEXT: 1 2 1.00 cmn.w r0, r1
+# CHECK-NEXT: 1 2 1.00 cmn.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 cmp r0, #1
+# CHECK-NEXT: 1 1 0.50 cmp.w r0, #1
+# CHECK-NEXT: 1 1 0.50 cmp r0, r1
+# CHECK-NEXT: 1 1 0.50 U cmp r0, r10
+# CHECK-NEXT: 1 2 1.00 cmp.w r0, r1
+# CHECK-NEXT: 1 2 1.00 cmp.w r0, r1, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U csdb
+# CHECK-NEXT: 1 2 1.00 csel r1, r2, r3, eq
+# CHECK-NEXT: 1 2 1.00 csinc r1, r2, r3, eq
+# CHECK-NEXT: 1 2 1.00 csinv r1, r2, r3, eq
+# CHECK-NEXT: 1 2 1.00 csneg r1, r2, r3, eq
+# CHECK-NEXT: 1 3 0.50 * * U dmb sy
+# CHECK-NEXT: 1 3 0.50 * * U dsb sy
+# CHECK-NEXT: 1 1 0.50 eor r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 eors r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 eors r0, r1
+# CHECK-NEXT: 1 2 1.00 eor.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 eors.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 eor.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 eors.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U esb.w
+# CHECK-NEXT: 1 3 0.50 * * U isb sy
+# CHECK-NEXT: 1 1 0.50 U lctp
+# CHECK-NEXT: 1 2 0.50 * lda r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * ldab r0, [r1]
+# CHECK-NEXT: 1 2 0.50 * * U ldaex r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * * U ldaexb r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * * U ldaexh r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * ldah r0, [r1]
+# CHECK-NEXT: 1 2 1.00 * ldm r0!, {r1}
+# CHECK-NEXT: 1 2 1.00 * ldm.w r0, {r1}
+# CHECK-NEXT: 1 2 1.00 * ldm.w r0, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r1, [r0], #4
+# CHECK-NEXT: 1 2 1.00 * ldmdb r0, {r1}
+# CHECK-NEXT: 1 2 1.00 * ldmdb r0!, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #4]
+# CHECK-NEXT: 1 3 0.50 * ldr r0, [sp, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #-1]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1], #1
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #1]!
+# CHECK-NEXT: 1 1 0.50 * ldr r0, [pc, #4]
+# CHECK-NEXT: 1 1 0.50 * ldr.w r0, [pc, #4]
+# CHECK-NEXT: 1 1 0.50 * ldr r0, next
+# CHECK-NEXT: 1 1 0.50 * ldr.w r0, next
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, r2]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, r2]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrb.w r0, [pc, #4]
+# CHECK-NEXT: 1 2 0.50 * ldrb.w r0, next
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrbt r0, [r1, #1]
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1]
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #-4]
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1], #4
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, [r1, #4]!
+# CHECK-NEXT: 1 2 1.00 * ldrd r0, r2, next
+# CHECK-NEXT: 1 2 0.50 * * U ldrex r0, [r1]
+# CHECK-NEXT: 1 2 0.50 * * U ldrex r0, [r1, #4]
+# CHECK-NEXT: 1 3 0.50 * * U ldrexb r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * * U ldrexh r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrh.w r0, [pc, #4]
+# CHECK-NEXT: 1 2 0.50 * ldrh.w r0, next
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrht r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrsb.w r0, [pc, #4]
+# CHECK-NEXT: 1 2 0.50 * ldrsb.w r0, next
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrsbt r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrsh.w r0, [pc, #4]
+# CHECK-NEXT: 1 2 0.50 * ldrsh.w r0, next
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrsht r0, [r1, #1]
+# CHECK-NEXT: 1 2 0.50 U ldrt r0, [r1, #1]
+# CHECK-NEXT: 0 0 0.00 U le lr, next
+# CHECK-NEXT: 0 4294967294 0.00 U le next
+# CHECK-NEXT: 0 0 0.00 U letp lr, next
+# CHECK-NEXT: 1 1 0.50 lsls r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsl.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsls.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsls r0, r1
+# CHECK-NEXT: 1 1 0.50 lsl.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 lsls.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 lsll r0, r1, #2
+# CHECK-NEXT: 1 2 1.00 lsll r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 lsrs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsr.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsrs.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 lsrs r0, r1
+# CHECK-NEXT: 1 1 0.50 lsr.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 lsrs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 lsrl r0, r1, #2
+# CHECK-NEXT: 1 2 1.00 mla r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 mls r0, r1, r2, r3
+# CHECK-NEXT: 1 1 0.50 movs r0, #1
+# CHECK-NEXT: 1 1 0.50 mov.w r0, #1
+# CHECK-NEXT: 1 1 0.50 movs.w r0, #1
+# CHECK-NEXT: 1 1 0.50 movw r0, #1
+# CHECK-NEXT: 1 1 0.50 mov r0, r1
+# CHECK-NEXT: 1 1 0.50 mov.w r0, r1
+# CHECK-NEXT: 1 1 0.50 movs.w r0, r1
+# CHECK-NEXT: 1 1 0.50 movt r0, #1
+# CHECK-NEXT: 1 3 0.50 U mrs r0, apsr
+# CHECK-NEXT: 1 3 0.50 U msr apsr_nzcvq, r0
+# CHECK-NEXT: 1 2 1.00 muls r1, r2, r1
+# CHECK-NEXT: 1 2 1.00 mul r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 mvn r0, #1
+# CHECK-NEXT: 1 1 0.50 mvns r0, #1
+# CHECK-NEXT: 1 1 0.50 mvns r0, r1
+# CHECK-NEXT: 1 2 1.00 mvn.w r0, r1
+# CHECK-NEXT: 1 2 1.00 mvns.w r0, r1
+# CHECK-NEXT: 1 2 1.00 mvn.w r0, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 mvns.w r0, r1, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U nop
+# CHECK-NEXT: 1 3 0.50 * * U nop.w
+# CHECK-NEXT: 1 1 0.50 orn r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orns r0, r1, #1
+# CHECK-NEXT: 1 2 1.00 orn r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orns r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orn r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 orns r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 orr r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orrs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orrs r0, r1
+# CHECK-NEXT: 1 2 1.00 orr.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orrs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orr.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 orrs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r2, r1
+# CHECK-NEXT: 1 2 1.00 pkhtb r0, r1, r2, asr #1
+# CHECK-NEXT: 1 2 1.00 * U pop {r0}
+# CHECK-NEXT: 1 2 1.00 * pop.w {r0, r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [sp], #4
+# CHECK-NEXT: 1 3 0.50 * * U pssbb
+# CHECK-NEXT: 1 3 1.00 * U push {r0}
+# CHECK-NEXT: 1 3 1.00 * push.w {r0, r1}
+# CHECK-NEXT: 1 3 0.50 * str r0, [sp, #-4]!
+# CHECK-NEXT: 1 2 1.00 qadd r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qadd16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qadd8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qasx r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 qdadd r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 qdsub r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsax r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 rbit r0, r1
+# CHECK-NEXT: 1 1 1.00 rev r0, r1
+# CHECK-NEXT: 1 1 1.00 rev.w r0, r1
+# CHECK-NEXT: 1 1 1.00 rev16 r0, r1
+# CHECK-NEXT: 1 1 1.00 rev16.w r0, r1
+# CHECK-NEXT: 1 1 1.00 revsh r0, r1
+# CHECK-NEXT: 1 1 1.00 revsh.w r0, r1
+# CHECK-NEXT: 1 1 0.50 ror.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 rors.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 rors r0, r1
+# CHECK-NEXT: 1 1 0.50 ror.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 rors.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 rrx r0, r1
+# CHECK-NEXT: 1 1 1.00 rrxs r0, r1
+# CHECK-NEXT: 1 1 0.50 rsbs r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 rsb.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 rsbs.w r0, r1, #1
+# CHECK-NEXT: 1 2 1.00 U rsb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 U rsbs r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 rsb r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 rsbs r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 1.00 * * U sadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U sadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U sasx r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 sbc r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 sbcs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 U sbcs r0, r1
+# CHECK-NEXT: 1 2 1.00 sbc.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sbcs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sbc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 sbcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 sbfx r0, r1, #1, #2
+# CHECK-NEXT: 2 8 1.00 sdiv r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * sel r0, r1, r2
+# CHECK-NEXT: 1 3 0.50 * * U sev
+# CHECK-NEXT: 1 1 1.00 shadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shasx r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smlabb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlabt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlatb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlatt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlad r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smladx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlalbb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlalbt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaltb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaltt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlald r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaldx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlawb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlawt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsd r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsdx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsld r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsldx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmla r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmlar r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 U smmls r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmlsr r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmul r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smmulr r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smuad r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smuadx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulbb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulbt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smultb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smultt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smull r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smulwb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulwt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smusd r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sqrshr r0, r1
+# CHECK-NEXT: 1 2 1.00 sqrshrl r0, r1, #48, r2
+# CHECK-NEXT: 1 2 1.00 sqshl r0, #7
+# CHECK-NEXT: 1 2 1.00 sqshll r0, r1, #7
+# CHECK-NEXT: 1 2 1.00 srshr r0, #7
+# CHECK-NEXT: 1 2 1.00 srshrl r0, r1, #7
+# CHECK-NEXT: 1 3 1.00 ssat r0, #1, r2
+# CHECK-NEXT: 1 3 1.00 ssat r0, #1, r2, lsl #1
+# CHECK-NEXT: 1 3 1.00 ssat16 r0, #1, r1
+# CHECK-NEXT: 1 1 1.00 * * U ssax r0, r1, r2
+# CHECK-NEXT: 1 3 0.50 * * U ssbb
+# CHECK-NEXT: 1 1 1.00 * * U ssub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2
+# CHECK-NEXT: 1 3 0.50 * stl r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * stlb r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * * U stlex r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * * U stlexb r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * * U stlexh r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * stlh r0, [r1]
+# CHECK-NEXT: 1 3 1.00 * stm r0!, {r1}
+# CHECK-NEXT: 1 3 1.00 * stm.w r0, {r1}
+# CHECK-NEXT: 1 3 1.00 * stm.w r0!, {r1}
+# CHECK-NEXT: 1 3 1.00 * stmdb r0, {r1}
+# CHECK-NEXT: 1 3 0.50 * str r1, [r0, #-4]!
+# CHECK-NEXT: 1 3 0.50 * str r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * str r0, [r1, #4]
+# CHECK-NEXT: 1 3 0.50 * str r0, [sp, #4]
+# CHECK-NEXT: 1 3 0.50 * str.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * str r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * str r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * str r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * str.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * str.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * strb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1, #1]!
+# CHECK-NEXT: 1 3 0.50 * strb r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * strb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * strb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U strbt r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2], #4
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]!
+# CHECK-NEXT: 1 3 0.50 * * U strex r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * * U strex r0, r1, [r2, #4]
+# CHECK-NEXT: 1 3 0.50 * * U strexb r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * * U strexh r0, r1, [r2]
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * strh.w r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1, #1]!
+# CHECK-NEXT: 1 3 0.50 * strh r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * strh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * strh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U strht r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 U strt r0, [r1, #1]
+# CHECK-NEXT: 1 2 0.50 U sub sp, #4
+# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 subw r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, r1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, r1
+# CHECK-NEXT: 1 2 1.00 sub.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 subs.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 subs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs r0, #1
+# CHECK-NEXT: 1 1 0.50 sub.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subw r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 sub.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 subs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sub.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 subs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 sxtab r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 sxtab16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 sxtah r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 1 1 1.00 sxtb r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb.w r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb.w r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 sxtb16 r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb16 r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 sxth r0, r1
+# CHECK-NEXT: 1 1 1.00 sxth.w r0, r1
+# CHECK-NEXT: 1 1 1.00 sxth.w r0, r1, ror #8
+# CHECK-NEXT: 1 2 0.50 U tbb [r0, r1]
+# CHECK-NEXT: 1 2 0.50 U tbh [r0, r1, lsl #1]
+# CHECK-NEXT: 1 1 0.50 teq.w r0, #1
+# CHECK-NEXT: 1 2 1.00 teq.w r0, r1
+# CHECK-NEXT: 1 2 1.00 teq.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 tst.w r0, #1
+# CHECK-NEXT: 1 1 0.50 tst r0, r1
+# CHECK-NEXT: 1 2 1.00 tst.w r0, r1
+# CHECK-NEXT: 1 2 1.00 tst.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 1.00 * * U uadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 ubfx r0, r1, #1, #2
+# CHECK-NEXT: 2 8 1.00 udiv r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 umaal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 umlal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 umull r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 uqadd16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqadd8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqasx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqrshl r0, r1
+# CHECK-NEXT: 1 2 1.00 uqrshll r0, r1, #48, r2
+# CHECK-NEXT: 1 2 1.00 uqsax r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqshl r0, #1
+# CHECK-NEXT: 1 2 1.00 uqshll r0, r1, #1
+# CHECK-NEXT: 1 2 1.00 uqsub16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 urshr r0, #1
+# CHECK-NEXT: 1 2 1.00 urshrl r0, r1, #1
+# CHECK-NEXT: 1 2 1.00 usad8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 usada8 r0, r1, r2, r3
+# CHECK-NEXT: 1 3 1.00 usat r0, #1, r1
+# CHECK-NEXT: 1 3 1.00 usat r0, #1, r1, lsl #1
+# CHECK-NEXT: 1 3 1.00 usat16 r0, #1, r1
+# CHECK-NEXT: 1 1 1.00 * * U usax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U usub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U usub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 uxtab16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 uxtah r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 1 1 1.00 uxtb r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb.w r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb.w r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 uxtb16 r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb16 r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 uxth r0, r1
+# CHECK-NEXT: 1 1 1.00 uxth.w r0, r1
+# CHECK-NEXT: 1 1 1.00 uxth.w r0, r1, ror #8
+# CHECK-NEXT: 1 3 0.50 * * U wfe
+# CHECK-NEXT: 1 3 0.50 * * U wfe.w
+# CHECK-NEXT: 1 3 0.50 * * U wfi
+# CHECK-NEXT: 1 3 0.50 * * U wfi.w
+# CHECK-NEXT: 1 1 0.50 U wls lr, r0, forward
+# CHECK-NEXT: 1 1 0.50 U dls lr, r0
+# CHECK-NEXT: 1 1 0.50 U wlstp.8 lr, r0, forward
+# CHECK-NEXT: 1 1 0.50 U wlstp.16 lr, r0, forward
+# CHECK-NEXT: 1 1 0.50 U wlstp.32 lr, r0, forward
+# CHECK-NEXT: 1 1 0.50 U wlstp.64 lr, r0, forward
+# CHECK-NEXT: 1 1 0.50 U dlstp.8 lr, r0
+# CHECK-NEXT: 1 1 0.50 U dlstp.16 lr, r0
+# CHECK-NEXT: 1 1 0.50 U dlstp.32 lr, r0
+# CHECK-NEXT: 1 1 0.50 U dlstp.64 lr, r0
+# CHECK-NEXT: 1 3 0.50 * * U yield
+# CHECK-NEXT: 1 3 0.50 * * U yield.w
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M85UnitALU
+# CHECK-NEXT: [0.1] - M85UnitALU
+# CHECK-NEXT: [1] - M85UnitBranch
+# CHECK-NEXT: [2] - M85UnitDiv
+# CHECK-NEXT: [3] - M85UnitLShift
+# CHECK-NEXT: [4] - M85UnitLoadH
+# CHECK-NEXT: [5] - M85UnitLoadL
+# CHECK-NEXT: [6] - M85UnitMAC
+# CHECK-NEXT: [7] - M85UnitSIMD
+# CHECK-NEXT: [8] - M85UnitShift1
+# CHECK-NEXT: [9] - M85UnitShift2
+# CHECK-NEXT: [10] - M85UnitSlot0
+# CHECK-NEXT: [11] - M85UnitStoreH
+# CHECK-NEXT: [12] - M85UnitStoreL
+# CHECK-NEXT: [13] - M85UnitVFPAH
+# CHECK-NEXT: [14] - M85UnitVFPAL
+# CHECK-NEXT: [15] - M85UnitVFPBH
+# CHECK-NEXT: [16] - M85UnitVFPBL
+# CHECK-NEXT: [17] - M85UnitVFPCH
+# CHECK-NEXT: [18] - M85UnitVFPCL
+# CHECK-NEXT: [19] - M85UnitVFPD
+# CHECK-NEXT: [20] - M85UnitVPortH
+# CHECK-NEXT: [21] - M85UnitVPortL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
+# CHECK-NEXT: 141.00 141.00 - 2.00 21.00 47.00 47.00 43.00 88.00 83.00 2.00 91.00 30.00 30.00 - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adc r0, r1, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adcs r0, r1, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adcs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adc.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adcs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w sp, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - addw r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add r0, sp, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - add.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adds.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds r0, #42
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - addw r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - add.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adds.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - add.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - adds.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adr.w r0, #-6
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adr.w r8, #-6
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - adr.w r0, #-6
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - and r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - ands r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - ands r1, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - and.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - ands.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - and.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - ands.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asrs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asr.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asrs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asrs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asr.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - asrs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - asrl r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - asrl r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - 1.00 - - - - - - - - - - - bfc r0, #1, #2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - 1.00 - - - - - - - - - - - bfi r0, r1, #1, #2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - bic r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - bics r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - bics r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - bic.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - bics.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - bic.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - bics.w r0, r1, r2, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - bkpt #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - clrex
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - clrm {r1, r2}
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 1.00 - - - - - - - - - - - clz r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmn.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmn r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - cmn.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - cmn.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmp r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmp.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmp r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - cmp r0, r10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - cmp.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - cmp.w r0, r1, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - csdb
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - csel r1, r2, r3, eq
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - csinc r1, r2, r3, eq
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - csinv r1, r2, r3, eq
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - csneg r1, r2, r3, eq
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - dmb sy
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - dsb sy
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - eor r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - eors r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - eors r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - eor.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - eors.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - eor.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - eors.w r0, r1, r2, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - esb.w
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - isb sy
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - lctp
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - lda r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldab r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldaex r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldaexb r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldaexh r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldah r0, [r1]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldm r0!, {r1}
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldm.w r0, {r1}
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldm.w r0, {r1}
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r1, [r0], #4
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldmdb r0, {r1}
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldmdb r0!, {r1}
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [r1, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [sp, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr.w r0, [r1, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [r1, #-1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [r1], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [r1, #1]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [pc, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr.w r0, [pc, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr.w r0, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldr.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb r0, [r1, #-1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb r0, [r1], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb r0, [r1, #1]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb.w r0, [pc, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb.w r0, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrbt r0, [r1, #1]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldrd r0, r2, [r1]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldrd r0, r2, [r1, #-4]
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldrd r0, r2, [r1], #4
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldrd r0, r2, [r1, #4]!
+# CHECK-NEXT: - - - - - 1.00 1.00 - - - - - - - - - - - - - - - - ldrd r0, r2, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrex r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrex r0, [r1, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrexb r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrexh r0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh r0, [r1, #2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh r0, [r1, #-1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh r0, [r1], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh r0, [r1, #1]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh.w r0, [pc, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh.w r0, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrht r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb r0, [r1, #-1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb r0, [r1], #1
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb r0, [r1, #1]!
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb.w r0, [pc, #4]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb.w r0, next
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsbt r0, [r1, #1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - ldrsh.w r0, [r1, #2]
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+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stl r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stlb r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stlex r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stlexb r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stlexh r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - stlh r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - stm r0!, {r1}
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - stm.w r0, {r1}
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - stm.w r0!, {r1}
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - stmdb r0, {r1}
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r1, [r0, #-4]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [r1, #4]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [sp, #4]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - str.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strbt r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - strd r0, r1, [r2, #4]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - strd r0, r1, [r2], #4
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 1.00 - - - - - - - - - strd r0, r1, [r2, #4]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strex r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strex r0, r1, [r2, #4]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strexb r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strexh r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1, #2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh.w r0, [r1, #2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1, #1]!
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strht r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - - - - - - strt r0, [r1, #1]
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - sub sp, #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - sub.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subw r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - sub.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - sub.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - subs.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - sub.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subw r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - sub.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - subs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - sub.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - subs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtab r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtab16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtah r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - sxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxtb r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxtb.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxtb.w r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxtb16 r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxtb16 r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxth r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxth.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - sxth.w r0, r1, ror #8
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - tbb [r0, r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - - - - - tbh [r0, r1, lsl #1]
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - teq.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - teq.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - teq.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - tst.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - tst r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - tst.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - 1.00 - - - - - - - - - - - - - tst.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - ubfx r0, r1, #1, #2
+# CHECK-NEXT: 0.50 0.50 - 1.00 - - - - - - - - - - - - - - - - - - - udiv r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uhsub8 r0, r1, r2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - - - - umaal r0, r1, r2, r3
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - - - - umlal r0, r1, r2, r3
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - - - - umull r0, r1, r2, r3
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - uqrshl r0, r1
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - uqrshll r0, r1, #48, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - uqshl r0, #1
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - uqshll r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uqsub8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - urshr r0, #1
+# CHECK-NEXT: 0.50 0.50 - - 1.00 - - - - - - - - - - - - - - - - - - urshrl r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - usad8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - usada8 r0, r1, r2, r3
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - usat r0, #1, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - usat r0, #1, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - usat16 r0, #1, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - usax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - usub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - usub8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtab r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtab16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtah r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 1.00 - 1.00 - - - - - - - - - - - uxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxtb r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxtb.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxtb.w r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxtb16 r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxtb16 r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxth r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxth.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - 1.00 - - - - - - - - - - - uxth.w r0, r1, ror #8
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wfe
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wfe.w
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wfi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wfi.w
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - wls lr, r0, forward
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - dls lr, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - wlstp.8 lr, r0, forward
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - wlstp.16 lr, r0, forward
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - wlstp.32 lr, r0, forward
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - wlstp.64 lr, r0, forward
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - dlstp.8 lr, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - dlstp.16 lr, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - dlstp.32 lr, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - - - - dlstp.64 lr, r0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - yield
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - yield.w
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s
new file mode 100644
index 00000000000000..57a885951056c9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s
@@ -0,0 +1,333 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s
+
+vabd.f16 q0, q2, q1
+vabd.f32 q0, q2, q1
+vabs.f16 q0, q2
+vabs.f32 q0, q2
+vadd.f16 q0, q2, q1
+vadd.f32 q0, q2, q1
+vadd.f16 q0, q2, r0
+vadd.f32 q0, q2, r0
+vcadd.f16 q0, q2, q1, #90
+vcadd.f32 q0, q2, q1, #90
+vcmla.f16 q0, q2, q1, #90
+vcmla.f32 q0, q2, q1, #90
+vcmul.f16 q0, q2, q1, #90
+vcmul.f32 q0, q2, q1, #90
+vcvt.f16.s16 q0, q1, #4
+vcvt.f16.u16 q0, q1, #4
+vcvt.s16.f16 q0, q1, #4
+vcvt.u16.f16 q0, q1, #4
+vcvt.f32.s32 q0, q1, #4
+vcvt.f32.u32 q0, q1, #4
+vcvt.s32.f32 q0, q1, #4
+vcvt.u32.f32 q0, q1, #4
+vcvt.f16.s16 q0, q1
+vcvt.f32.s32 q0, q1
+vcvt.f16.u16 q0, q1
+vcvt.f32.u32 q0, q1
+vcvt.s16.f16 q0, q1
+vcvt.s32.f32 q0, q1
+vcvt.u16.f16 q0, q1
+vcvt.u32.f32 q0, q1
+vcvtb.f16.f32 q0, q1
+vcvtb.f32.f16 q0, q1
+vcvtt.f16.f32 q0, q1
+vcvtt.f32.f16 q0, q1
+vcvta.s16.f16 q0, q1
+vcvta.s32.f32 q0, q1
+vcvta.u16.f16 q0, q1
+vcvta.u32.f32 q0, q1
+vcvtm.s16.f16 q0, q1
+vcvtm.s32.f32 q0, q1
+vcvtm.u16.f16 q0, q1
+vcvtm.u32.f32 q0, q1
+vcvtn.s16.f16 q0, q1
+vcvtn.s32.f32 q0, q1
+vcvtn.u16.f16 q0, q1
+vcvtn.u32.f32 q0, q1
+vcvtp.s16.f16 q0, q1
+vcvtp.s32.f32 q0, q1
+vcvtp.u16.f16 q0, q1
+vcvtp.u32.f32 q0, q1
+vfma.f16 q0, q2, r0
+vfma.f32 q0, q2, r0
+vfma.f16 q0, q2, q1
+vfma.f32 q0, q2, q1
+vfms.f16 q0, q2, q1
+vfms.f32 q0, q2, q1
+vfmas.f16 q0, q2, r0
+vfmas.f32 q0, q2, r0
+vmaxnm.f16 q0, q2, q1
+vmaxnm.f32 q0, q2, q1
+vmaxnma.f16 q0, q2
+vmaxnma.f32 q0, q2
+vmaxnmv.f16 r0, q2
+vmaxnmv.f32 r0, q2
+vmaxnmav.f16 r0, q2
+vmaxnmav.f32 r0, q2
+vminnm.f16 q0, q2, q1
+vminnm.f32 q0, q2, q1
+vminnma.f16 q0, q2
+vminnma.f32 q0, q2
+vminnmv.f16 r0, q2
+vminnmv.f32 r0, q2
+vminnmav.f16 r0, q2
+vminnmav.f32 r0, q2
+vmul.f16 q0, q2, q1
+vmul.f32 q0, q2, q1
+vmul.f16 q0, q2, r0
+vmul.f32 q0, q2, r0
+vneg.f16 q0, q2
+vneg.f32 q0, q2
+vrinta.f16 q0, q2
+vrinta.f32 q0, q2
+vrintm.f16 q0, q2
+vrintm.f32 q0, q2
+vrintn.f16 q0, q2
+vrintn.f32 q0, q2
+vrintp.f16 q0, q2
+vrintp.f32 q0, q2
+vrintx.f16 q0, q2
+vrintx.f32 q0, q2
+vrintz.f16 q0, q2
+vrintz.f32 q0, q2
+vsub.f16 q0, q2, q1
+vsub.f32 q0, q2, q1
+vsub.f16 q0, q2, r0
+vsub.f32 q0, q2, r0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 2.00 vabd.f16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vabd.f32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabs.f16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vabs.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vadd.f16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vadd.f32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vadd.f16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vadd.f32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vcadd.f16 q0, q2, q1, #90
+# CHECK-NEXT: 1 2 2.00 vcadd.f32 q0, q2, q1, #90
+# CHECK-NEXT: 1 4 2.00 vcmla.f16 q0, q2, q1, #90
+# CHECK-NEXT: 1 4 2.00 vcmla.f32 q0, q2, q1, #90
+# CHECK-NEXT: 1 3 2.00 vcmul.f16 q0, q2, q1, #90
+# CHECK-NEXT: 1 3 2.00 vcmul.f32 q0, q2, q1, #90
+# CHECK-NEXT: 1 2 2.00 vcvt.f16.s16 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.f16.u16 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.s16.f16 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.u16.f16 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.f32.s32 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.f32.u32 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.s32.f32 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.u32.f32 q0, q1, #4
+# CHECK-NEXT: 1 2 2.00 vcvt.f16.s16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.f32.s32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.f16.u16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.f32.u32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.s16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.s32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.u16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvt.u32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtb.f16.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtb.f32.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtt.f16.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtt.f32.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvta.s16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvta.s32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvta.u16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvta.u32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtm.s16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtm.s32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtm.u16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtm.u32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtn.s16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtn.s32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtn.u16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtn.u32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtp.s16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtp.s32.f32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtp.u16.f16 q0, q1
+# CHECK-NEXT: 1 2 2.00 vcvtp.u32.f32 q0, q1
+# CHECK-NEXT: 1 4 2.00 vfma.f16 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vfma.f32 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vfma.f16 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vfma.f32 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vfms.f16 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vfms.f32 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vfmas.f16 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vfmas.f32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vmaxnm.f16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmaxnm.f32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmaxnma.f16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vmaxnma.f32 q0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxnmv.f16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxnmv.f32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxnmav.f16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxnmav.f32 r0, q2
+# CHECK-NEXT: 1 1 2.00 vminnm.f16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vminnm.f32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vminnma.f16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vminnma.f32 q0, q2
+# CHECK-NEXT: 1 4 2.00 vminnmv.f16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminnmv.f32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminnmav.f16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminnmav.f32 r0, q2
+# CHECK-NEXT: 1 3 2.00 vmul.f16 q0, q2, q1
+# CHECK-NEXT: 1 3 2.00 vmul.f32 q0, q2, q1
+# CHECK-NEXT: 1 3 2.00 vmul.f16 q0, q2, r0
+# CHECK-NEXT: 1 3 2.00 vmul.f32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vneg.f16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vneg.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrinta.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrinta.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintm.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintm.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintn.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintn.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintp.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintp.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintx.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintx.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintz.f16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vrintz.f32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vsub.f16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vsub.f32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vsub.f16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vsub.f32 q0, q2, r0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M85UnitALU
+# CHECK-NEXT: [0.1] - M85UnitALU
+# CHECK-NEXT: [1] - M85UnitBranch
+# CHECK-NEXT: [2] - M85UnitDiv
+# CHECK-NEXT: [3] - M85UnitLShift
+# CHECK-NEXT: [4] - M85UnitLoadH
+# CHECK-NEXT: [5] - M85UnitLoadL
+# CHECK-NEXT: [6] - M85UnitMAC
+# CHECK-NEXT: [7] - M85UnitSIMD
+# CHECK-NEXT: [8] - M85UnitShift1
+# CHECK-NEXT: [9] - M85UnitShift2
+# CHECK-NEXT: [10] - M85UnitSlot0
+# CHECK-NEXT: [11] - M85UnitStoreH
+# CHECK-NEXT: [12] - M85UnitStoreL
+# CHECK-NEXT: [13] - M85UnitVFPAH
+# CHECK-NEXT: [14] - M85UnitVFPAL
+# CHECK-NEXT: [15] - M85UnitVFPBH
+# CHECK-NEXT: [16] - M85UnitVFPBL
+# CHECK-NEXT: [17] - M85UnitVFPCH
+# CHECK-NEXT: [18] - M85UnitVFPCL
+# CHECK-NEXT: [19] - M85UnitVFPD
+# CHECK-NEXT: [20] - M85UnitVPortH
+# CHECK-NEXT: [21] - M85UnitVPortL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
+# CHECK-NEXT: - - - - - - - - - - - 96.00 - - 24.00 24.00 168.00 168.00 - - - 96.00 96.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vabs.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vabs.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.f16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.f32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vcadd.f16 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vcadd.f32 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcmla.f16 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcmla.f32 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcmul.f16 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcmul.f32 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f16.s16 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f16.u16 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.s16.f16 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.u16.f16 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f32.s32 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f32.u32 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.s32.f32 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.u32.f32 q0, q1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f16.s16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f32.s32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f16.u16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.f32.u32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.s16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.s32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.u16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvt.u32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtb.f16.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtb.f32.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtt.f16.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtt.f32.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvta.s16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvta.s32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvta.u16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvta.u32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtm.s16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtm.s32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtm.u16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtm.u32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtn.s16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtn.s32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtn.u16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtn.u32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtp.s16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtp.s32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtp.u16.f16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vcvtp.u32.f32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfma.f16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfma.f32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfma.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfma.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfms.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfms.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfmas.f16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vfmas.f32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnm.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnm.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnma.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnma.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnmv.f16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnmv.f32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnmav.f16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmaxnmav.f32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnm.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnm.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnma.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnma.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnmv.f16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnmv.f32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnmav.f16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vminnmav.f32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.f16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.f32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vneg.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vneg.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrinta.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrinta.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintm.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintm.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintn.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintn.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintp.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintp.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintx.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintx.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintz.f16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrintz.f32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.f16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.f32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.f16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.f32 q0, q2, r0
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s
new file mode 100644
index 00000000000000..a98dec28f79bff
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s
@@ -0,0 +1,1584 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s
+
+vabav.s8 r0, q2, q1
+vabav.u8 r0, q2, q1
+vabav.s16 r0, q2, q1
+vabav.u16 r0, q2, q1
+vabav.s32 r0, q2, q1
+vabav.u32 r0, q2, q1
+vabd.s8 q0, q2, q1
+vabd.u8 q0, q2, q1
+vabd.s16 q0, q2, q1
+vabd.u16 q0, q2, q1
+vabd.s32 q0, q2, q1
+vabd.u32 q0, q2, q1
+vabs.s8 q0, q2
+vabs.s16 q0, q2
+vabs.s32 q0, q2
+vadc.i32 q0, q2, q1
+vadci.i32 q0, q2, q1
+vadd.i8 q0, q2, q1
+vadd.i16 q0, q2, q1
+vadd.i32 q0, q2, q1
+vadd.i8 q0, q2, r0
+vadd.i16 q0, q2, r0
+vadd.i32 q0, q2, r0
+vaddlv.s32 r0, r1, q1
+vaddlv.u32 r0, r1, q1
+vaddlva.s32 r0, r1, q1
+vaddlva.u32 r0, r1, q1
+vaddv.s8 r0, q1
+vaddv.u8 r0, q1
+vaddv.s16 r0, q1
+vaddv.u16 r0, q1
+vaddv.s32 r0, q1
+vaddv.u32 r0, q1
+vaddva.s8 r0, q1
+vaddva.u8 r0, q1
+vaddva.s16 r0, q1
+vaddva.u16 r0, q1
+vaddva.s32 r0, q1
+vaddva.u32 r0, q1
+vand q0, q2, q1
+vbic.i16 q0, #10
+vbic.i32 q0, #10
+vbic q0, q2, q1
+vbrsr.8 q0, q2, r0
+vbrsr.16 q0, q2, r0
+vbrsr.32 q0, q2, r0
+vcadd.i8 q0, q2, q1, #90
+vcadd.i16 q0, q2, q1, #90
+vcadd.i32 q0, q2, q1, #90
+vcls.s8 q0, q2
+vcls.s16 q0, q2
+vcls.s32 q0, q2
+vclz.i8 q0, q2
+vclz.i16 q0, q2
+vclz.i32 q0, q2
+vdwdup.u8 q0, r0, r1, #4
+vdwdup.u16 q0, r0, r1, #4
+vdwdup.u32 q0, r0, r1, #4
+vddup.u8 q0, r0, #4
+vddup.u16 q0, r0, #4
+vddup.u32 q0, r0, #4
+vdup.8 q0, r0
+vdup.16 q0, r0
+vdup.32 q0, r0
+veor q0, q2, q1
+vhadd.s8 q0, q2, q1
+vhadd.u8 q0, q2, q1
+vhadd.s16 q0, q2, q1
+vhadd.u16 q0, q2, q1
+vhadd.s32 q0, q2, q1
+vhadd.u32 q0, q2, q1
+vhadd.s8 q0, q2, r0
+vhadd.u8 q0, q2, r0
+vhadd.s16 q0, q2, r0
+vhadd.u16 q0, q2, r0
+vhadd.s32 q0, q2, r0
+vhadd.u32 q0, q2, r0
+vhcadd.s8 q0, q2, q1, #90
+vhcadd.s16 q0, q2, q1, #90
+vhcadd.s32 q0, q2, q1, #90
+vhsub.s8 q0, q2, q1
+vhsub.u8 q0, q2, q1
+vhsub.s16 q0, q2, q1
+vhsub.u16 q0, q2, q1
+vhsub.s32 q0, q2, q1
+vhsub.u32 q0, q2, q1
+vhsub.s8 q0, q2, r0
+vhsub.u8 q0, q2, r0
+vhsub.s16 q0, q2, r0
+vhsub.u16 q0, q2, r0
+vhsub.s32 q0, q2, r0
+vhsub.u32 q0, q2, r0
+viwdup.u8 q0, r0, r1, #4
+viwdup.u16 q0, r0, r1, #4
+viwdup.u32 q0, r0, r1, #4
+vidup.u8 q0, r0, #4
+vidup.u16 q0, r0, #4
+vidup.u32 q0, r0, #4
+vmax.s8 q0, q2, q1
+vmax.u8 q0, q2, q1
+vmax.s16 q0, q2, q1
+vmax.u16 q0, q2, q1
+vmax.s32 q0, q2, q1
+vmax.u32 q0, q2, q1
+vmaxa.s8 q0, q2
+vmaxa.s16 q0, q2
+vmaxa.s32 q0, q2
+vmaxv.s8 r0, q2
+vmaxv.u8 r0, q2
+vmaxv.s16 r0, q2
+vmaxv.u16 r0, q2
+vmaxv.s32 r0, q2
+vmaxv.u32 r0, q2
+vmaxav.s8 r0, q2
+vmaxav.s16 r0, q2
+vmaxav.s32 r0, q2
+vmin.s8 q0, q2, q1
+vmin.u8 q0, q2, q1
+vmin.s16 q0, q2, q1
+vmin.u16 q0, q2, q1
+vmin.s32 q0, q2, q1
+vmin.u32 q0, q2, q1
+vmina.s8 q0, q2
+vmina.s16 q0, q2
+vmina.s32 q0, q2
+vminv.s8 r0, q2
+vminv.u8 r0, q2
+vminv.s16 r0, q2
+vminv.u16 r0, q2
+vminv.s32 r0, q2
+vminv.u32 r0, q2
+vminav.s8 r0, q2
+vminav.s16 r0, q2
+vminav.s32 r0, q2
+vmla.i8 q0, q2, r0
+vmla.i16 q0, q2, r0
+vmla.i32 q0, q2, r0
+vmladav.s8 r0, q2, q1
+vmladav.u8 r0, q2, q1
+vmladav.s16 r0, q2, q1
+vmladav.u16 r0, q2, q1
+vmladav.s32 r0, q2, q1
+vmladav.u32 r0, q2, q1
+vmladava.s8 r0, q2, q1
+vmladava.u8 r0, q2, q1
+vmladava.s16 r0, q2, q1
+vmladava.u16 r0, q2, q1
+vmladava.s32 r0, q2, q1
+vmladava.u32 r0, q2, q1
+vmladavax.s8 r0, q2, q1
+vmladavax.s16 r0, q2, q1
+vmladavax.s32 r0, q2, q1
+vmladavx.s8 r0, q2, q1
+vmladavx.s16 r0, q2, q1
+vmladavx.s32 r0, q2, q1
+vmlaldav.s16 r0, r1, q2, q1
+vmlaldav.u16 r0, r1, q2, q1
+vmlaldav.s32 r0, r1, q2, q1
+vmlaldav.u32 r0, r1, q2, q1
+vmlaldava.s16 r0, r1, q2, q1
+vmlaldava.u16 r0, r1, q2, q1
+vmlaldava.s32 r0, r1, q2, q1
+vmlaldava.u32 r0, r1, q2, q1
+vmlaldavax.s16 r0, r1, q2, q1
+vmlaldavax.s32 r0, r1, q2, q1
+vmlaldavx.s16 r0, r1, q2, q1
+vmlaldavx.s32 r0, r1, q2, q1
+vmlas.i8 q0, q2, r0
+vmlas.i16 q0, q2, r0
+vmlas.i32 q0, q2, r0
+vmlsdav.s8 r0, q2, q1
+vmlsdav.s16 r0, q2, q1
+vmlsdav.s32 r0, q2, q1
+vmlsdava.s8 r0, q2, q1
+vmlsdava.s16 r0, q2, q1
+vmlsdava.s32 r0, q2, q1
+vmlsdavax.s8 r0, q2, q1
+vmlsdavax.s16 r0, q2, q1
+vmlsdavax.s32 r0, q2, q1
+vmlsdavx.s8 r0, q2, q1
+vmlsdavx.s16 r0, q2, q1
+vmlsdavx.s32 r0, q2, q1
+vmlsldav.s16 r0, r1, q2, q1
+vmlsldav.s32 r0, r1, q2, q1
+vmlsldava.s16 r0, r1, q2, q1
+vmlsldava.s32 r0, r1, q2, q1
+vmlsldavax.s16 r0, r1, q2, q1
+vmlsldavax.s32 r0, r1, q2, q1
+vmlsldavx.s16 r0, r1, q2, q1
+vmlsldavx.s32 r0, r1, q2, q1
+vmov.8 q0[1], r0
+vmov.16 q0[1], r0
+vmov.32 q0[1], r0
+vmov.i8 q0, #0
+vmov.i16 q0, #0
+vmov.i32 q0, #0
+vmov.i64 q0, #0
+vmov.f32 q0, #1.0
+vmov r1, r2, q0[2], q0[0]
+vmov q0[2], q0[0], r1, r2
+vmov.32 r0, q0[1]
+vmov.s16 r0, q0[1]
+vmov.u16 r0, q0[1]
+vmov.s8 r0, q0[1]
+vmov.u8 r0, q0[1]
+vmovlb.s8 q0, q1
+vmovlb.u8 q0, q1
+vmovlb.s16 q0, q1
+vmovlb.u16 q0, q1
+vmovlt.s8 q0, q1
+vmovlt.u8 q0, q1
+vmovlt.s16 q0, q1
+vmovlt.u16 q0, q1
+vmovnb.i16 q0, q1
+vmovnb.i32 q0, q1
+vmovnt.i16 q0, q1
+vmovnt.i32 q0, q1
+vmul.i8 q0, q2, q1
+vmul.i16 q0, q2, q1
+vmul.i32 q0, q2, q1
+vmul.i8 q0, q2, r0
+vmul.i16 q0, q2, r0
+vmul.i32 q0, q2, r0
+vmulh.s8 q0, q2, q1
+vmulh.u8 q0, q2, q1
+vmulh.s16 q0, q2, q1
+vmulh.u16 q0, q2, q1
+vmulh.s32 q0, q2, q1
+vmulh.u32 q0, q2, q1
+vrmulh.s8 q0, q2, q1
+vrmulh.u8 q0, q2, q1
+vrmulh.s16 q0, q2, q1
+vrmulh.u16 q0, q2, q1
+vrmulh.s32 q0, q2, q1
+vrmulh.u32 q0, q2, q1
+vmullb.s8 q0, q2, q1
+vmullb.u8 q0, q2, q1
+vmullb.s16 q0, q2, q1
+vmullb.u16 q0, q2, q1
+vmullb.s32 q0, q2, q1
+vmullb.u32 q0, q2, q1
+vmullt.s8 q0, q2, q1
+vmullt.u8 q0, q2, q1
+vmullt.s16 q0, q2, q1
+vmullt.u16 q0, q2, q1
+vmullt.s32 q0, q2, q1
+vmullt.u32 q0, q2, q1
+vmullb.p8 q0, q2, q1
+vmullb.p16 q0, q2, q1
+vmullt.p8 q0, q2, q1
+vmullt.p16 q0, q2, q1
+vmvn.i16 q0, #10
+vmvn.i32 q0, #10
+vmvn q0, q2
+vneg.s8 q0, q2
+vneg.s16 q0, q2
+vneg.s32 q0, q2
+vorn q0, q2, q1
+vorr.i16 q0, #10
+vorr.i32 q0, #10
+vorr q0, q2, q1
+vpsel q0, q2, q1
+vqabs.s8 q0, q2
+vqabs.s16 q0, q2
+vqabs.s32 q0, q2
+vqadd.s8 q0, q2, q1
+vqadd.u8 q0, q2, q1
+vqadd.s16 q0, q2, q1
+vqadd.u16 q0, q2, q1
+vqadd.s32 q0, q2, q1
+vqadd.u32 q0, q2, q1
+vqadd.s8 q0, q2, r0
+vqadd.u8 q0, q2, r0
+vqadd.s16 q0, q2, r0
+vqadd.u16 q0, q2, r0
+vqadd.s32 q0, q2, r0
+vqadd.u32 q0, q2, r0
+vqdmladh.s8 q0, q2, q1
+vqdmladh.s16 q0, q2, q1
+vqdmladh.s32 q0, q2, q1
+vqdmladhx.s8 q0, q2, q1
+vqdmladhx.s16 q0, q2, q1
+vqdmladhx.s32 q0, q2, q1
+vqrdmladh.s8 q0, q2, q1
+vqrdmladh.s16 q0, q2, q1
+vqrdmladh.s32 q0, q2, q1
+vqrdmladhx.s8 q0, q2, q1
+vqrdmladhx.s16 q0, q2, q1
+vqrdmladhx.s32 q0, q2, q1
+vqdmlah.s8 q0, q2, r0
+vqdmlah.s16 q0, q2, r0
+vqdmlah.s32 q0, q2, r0
+vqrdmlah.s8 q0, q2, r0
+vqrdmlah.s16 q0, q2, r0
+vqrdmlah.s32 q0, q2, r0
+vqdmlash.s8 q0, q2, r0
+vqdmlash.s16 q0, q2, r0
+vqdmlash.s32 q0, q2, r0
+vqrdmlash.s8 q0, q2, r0
+vqrdmlash.s16 q0, q2, r0
+vqrdmlash.s32 q0, q2, r0
+vqdmlsdh.s8 q0, q2, q1
+vqdmlsdh.s16 q0, q2, q1
+vqdmlsdh.s32 q0, q2, q1
+vqdmlsdhx.s8 q0, q2, q1
+vqdmlsdhx.s16 q0, q2, q1
+vqdmlsdhx.s32 q0, q2, q1
+vqrdmlsdh.s8 q0, q2, q1
+vqrdmlsdh.s16 q0, q2, q1
+vqrdmlsdh.s32 q0, q2, q1
+vqrdmlsdhx.s8 q0, q2, q1
+vqrdmlsdhx.s16 q0, q2, q1
+vqrdmlsdhx.s32 q0, q2, q1
+vqdmulh.s8 q0, q2, q1
+vqdmulh.s16 q0, q2, q1
+vqdmulh.s32 q0, q2, q1
+vqrdmulh.s8 q0, q2, q1
+vqrdmulh.s16 q0, q2, q1
+vqrdmulh.s32 q0, q2, q1
+vqdmulh.s8 q0, q2, r0
+vqdmulh.s16 q0, q2, r0
+vqdmulh.s32 q0, q2, r0
+vqrdmulh.s8 q0, q2, r0
+vqrdmulh.s16 q0, q2, r0
+vqrdmulh.s32 q0, q2, r0
+vqdmullt.s16 q0, q2, q1
+vqdmullt.s32 q0, q2, q1
+vqdmullb.s16 q0, q2, r0
+vqdmullb.s32 q0, q2, r0
+vqmovnt.s16 q0, q2
+vqmovnt.u16 q0, q2
+vqmovnt.s32 q0, q2
+vqmovnt.u32 q0, q2
+vqmovnb.s16 q0, q2
+vqmovnb.u16 q0, q2
+vqmovnb.s32 q0, q2
+vqmovnb.u32 q0, q2
+vqmovunt.s16 q0, q2
+vqmovunt.s32 q0, q2
+vqmovunb.s16 q0, q2
+vqmovunb.s32 q0, q2
+vqneg.s8 q0, q2
+vqneg.s16 q0, q2
+vqneg.s32 q0, q2
+vqrshl.s8 q0, q2, q1
+vqrshl.u8 q0, q2, q1
+vqrshl.s16 q0, q2, q1
+vqrshl.u16 q0, q2, q1
+vqrshl.s32 q0, q2, q1
+vqrshl.u32 q0, q2, q1
+vqrshl.s8 q0, r0
+vqrshl.u8 q0, r0
+vqrshl.s16 q0, r0
+vqrshl.u16 q0, r0
+vqrshl.s32 q0, r0
+vqrshl.u32 q0, r0
+vqrshrnb.s16 q0, q2, #5
+vqrshrnb.u16 q0, q2, #5
+vqrshrnb.s32 q0, q2, #5
+vqrshrnb.u32 q0, q2, #5
+vqrshrnt.s16 q0, q2, #5
+vqrshrnt.u16 q0, q2, #5
+vqrshrnt.s32 q0, q2, #5
+vqrshrnt.u32 q0, q2, #5
+vqrshrunb.s16 q0, q2, #5
+vqrshrunb.s32 q0, q2, #5
+vqrshrunt.s16 q0, q2, #5
+vqrshrunt.s32 q0, q2, #5
+vqshl.s8 q0, r0
+vqshl.u8 q0, r0
+vqshl.s16 q0, r0
+vqshl.u16 q0, r0
+vqshl.s32 q0, r0
+vqshl.u32 q0, r0
+vqshl.s8 q0, q2, #5
+vqshl.u8 q0, q2, #5
+vqshl.s16 q0, q2, #5
+vqshl.u16 q0, q2, #5
+vqshl.s32 q0, q2, #5
+vqshl.u32 q0, q2, #5
+vqshlu.s8 q0, q2, #5
+vqshlu.s16 q0, q2, #5
+vqshlu.s32 q0, q2, #5
+vqshl.s8 q0, q2, q1
+vqshl.u8 q0, q2, q1
+vqshl.s16 q0, q2, q1
+vqshl.u16 q0, q2, q1
+vqshl.s32 q0, q2, q1
+vqshl.u32 q0, q2, q1
+vqshrnb.s16 q0, q2, #5
+vqshrnb.u16 q0, q2, #5
+vqshrnb.s32 q0, q2, #5
+vqshrnb.u32 q0, q2, #5
+vqshrnt.s16 q0, q2, #5
+vqshrnt.u16 q0, q2, #5
+vqshrnt.s32 q0, q2, #5
+vqshrnt.u32 q0, q2, #5
+vqshrunb.s16 q0, q2, #5
+vqshrunb.s32 q0, q2, #5
+vqshrunt.s16 q0, q2, #5
+vqshrunt.s32 q0, q2, #5
+vqsub.s8 q0, q2, q1
+vqsub.u8 q0, q2, q1
+vqsub.s16 q0, q2, q1
+vqsub.u16 q0, q2, q1
+vqsub.s32 q0, q2, q1
+vqsub.u32 q0, q2, q1
+vqsub.s8 q0, q2, r0
+vqsub.u8 q0, q2, r0
+vqsub.s16 q0, q2, r0
+vqsub.u16 q0, q2, r0
+vqsub.s32 q0, q2, r0
+vqsub.u32 q0, q2, r0
+vrev16.8 q0, q2
+vrev32.8 q0, q2
+vrev32.16 q0, q2
+vrev64.8 q0, q2
+vrev64.16 q0, q2
+vrev64.32 q0, q2
+vrhadd.s8 q0, q2, q1
+vrhadd.u8 q0, q2, q1
+vrhadd.s16 q0, q2, q1
+vrhadd.u16 q0, q2, q1
+vrhadd.s32 q0, q2, q1
+vrhadd.u32 q0, q2, q1
+vrmlaldavh.s32 r0, r1, q2, q1
+vrmlaldavh.u32 r0, r1, q2, q1
+vrmlaldavha.s32 r0, r1, q2, q1
+vrmlaldavha.u32 r0, r1, q2, q1
+vrmlaldavhx.s32 r0, r1, q2, q1
+vrmlaldavhax.s32 r0, r1, q2, q1
+vrmlsldavh.s32 r0, r1, q2, q1
+vrmlsldavha.s32 r0, r1, q2, q1
+vrmlsldavhx.s32 r0, r1, q2, q1
+vrmlsldavhax.s32 r0, r1, q2, q1
+vrshl.s8 q0, q2, q1
+vrshl.u8 q0, q2, q1
+vrshl.s16 q0, q2, q1
+vrshl.u16 q0, q2, q1
+vrshl.s32 q0, q2, q1
+vrshl.u32 q0, q2, q1
+vrshl.s8 q0, r0
+vrshl.u8 q0, r0
+vrshl.s16 q0, r0
+vrshl.u16 q0, r0
+vrshl.s32 q0, r0
+vrshl.u32 q0, r0
+vrshr.s8 q0, q2, #5
+vrshr.u8 q0, q2, #5
+vrshr.s16 q0, q2, #5
+vrshr.u16 q0, q2, #5
+vrshr.s32 q0, q2, #5
+vrshr.u32 q0, q2, #5
+vrshrnb.i16 q0, q2, #5
+vrshrnb.i32 q0, q2, #5
+vrshrnt.i16 q0, q2, #5
+vrshrnt.i32 q0, q2, #5
+vsbc.i32 q0, q2, q1
+vsbci.i32 q0, q2, q1
+vshl.i8 q0, q2, #1
+vshl.i16 q0, q2, #1
+vshl.i32 q0, q2, #1
+vshl.s8 q0, r0
+vshl.u8 q0, r0
+vshl.s16 q0, r0
+vshl.u16 q0, r0
+vshl.s32 q0, r0
+vshl.u32 q0, r0
+vshl.s8 q0, q2, q1
+vshl.u8 q0, q2, q1
+vshl.s16 q0, q2, q1
+vshl.u16 q0, q2, q1
+vshl.s32 q0, q2, q1
+vshl.u32 q0, q2, q1
+vshlc q0, r0, #5
+vshllt.s8 q0, q2, #5
+vshllt.u8 q0, q2, #5
+vshllt.s16 q0, q2, #5
+vshllt.u16 q0, q2, #5
+vshllb.s8 q0, q2, #5
+vshllb.u8 q0, q2, #5
+vshllb.s16 q0, q2, #5
+vshllb.u16 q0, q2, #5
+vshllt.s8 q0, q2, #8
+vshllt.u8 q0, q2, #8
+vshllt.s16 q0, q2, #16
+vshllt.u16 q0, q2, #16
+vshllb.s8 q0, q2, #8
+vshllb.u8 q0, q2, #8
+vshllb.s16 q0, q2, #16
+vshllb.u16 q0, q2, #16
+vshr.s8 q0, q2, #5
+vshr.u8 q0, q2, #5
+vshr.s16 q0, q2, #5
+vshr.u16 q0, q2, #5
+vshr.s32 q0, q2, #5
+vshr.u32 q0, q2, #5
+vshrnb.i16 q0, q2, #5
+vshrnb.i32 q0, q2, #5
+vshrnt.i16 q0, q2, #5
+vshrnt.i32 q0, q2, #5
+vsli.8 q0, q2, #5
+vsli.16 q0, q2, #5
+vsli.32 q0, q2, #5
+vsri.8 q0, q2, #5
+vsri.16 q0, q2, #5
+vsri.32 q0, q2, #5
+vsub.i8 q0, q2, q1
+vsub.i16 q0, q2, q1
+vsub.i32 q0, q2, q1
+vsub.i8 q0, q2, r0
+vsub.i16 q0, q2, r0
+vsub.i32 q0, q2, r0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 2.00 vabav.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vabav.u8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vabav.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vabav.u16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vabav.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vabav.u32 r0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabd.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vabs.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vabs.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vabs.s32 q0, q2
+# CHECK-NEXT: 1 3 2.00 U vadc.i32 q0, q2, q1
+# CHECK-NEXT: 1 3 2.00 U vadci.i32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vadd.i8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vadd.i16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vadd.i32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vadd.i8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vadd.i16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vadd.i32 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vaddlv.s32 r0, r1, q1
+# CHECK-NEXT: 1 4 2.00 vaddlv.u32 r0, r1, q1
+# CHECK-NEXT: 1 4 2.00 vaddlva.s32 r0, r1, q1
+# CHECK-NEXT: 1 4 2.00 vaddlva.u32 r0, r1, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.s8 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.u8 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.s16 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.u16 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.s32 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddv.u32 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.s8 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.u8 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.s16 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.u16 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.s32 r0, q1
+# CHECK-NEXT: 1 4 2.00 vaddva.u32 r0, q1
+# CHECK-NEXT: 1 1 1.00 vand q0, q2, q1
+# CHECK-NEXT: 1 1 1.00 vbic.i16 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vbic.i32 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vbic q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vbrsr.8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vbrsr.16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vbrsr.32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vcadd.i8 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 2.00 vcadd.i16 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 2.00 vcadd.i32 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 1.00 vcls.s8 q0, q2
+# CHECK-NEXT: 1 1 1.00 vcls.s16 q0, q2
+# CHECK-NEXT: 1 1 1.00 vcls.s32 q0, q2
+# CHECK-NEXT: 1 1 1.00 vclz.i8 q0, q2
+# CHECK-NEXT: 1 1 1.00 vclz.i16 q0, q2
+# CHECK-NEXT: 1 1 1.00 vclz.i32 q0, q2
+# CHECK-NEXT: 1 4 2.00 vdwdup.u8 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 vdwdup.u16 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 vdwdup.u32 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 vddup.u8 q0, r0, #4
+# CHECK-NEXT: 1 4 2.00 vddup.u16 q0, r0, #4
+# CHECK-NEXT: 1 4 2.00 vddup.u32 q0, r0, #4
+# CHECK-NEXT: 1 1 2.00 vdup.8 q0, r0
+# CHECK-NEXT: 1 1 2.00 vdup.16 q0, r0
+# CHECK-NEXT: 1 1 2.00 vdup.32 q0, r0
+# CHECK-NEXT: 1 1 1.00 veor q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhadd.s8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhadd.u8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhadd.s16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhadd.u16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhadd.s32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhadd.u32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhcadd.s8 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 2.00 vhcadd.s16 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 2.00 vhcadd.s32 q0, q2, q1, #90
+# CHECK-NEXT: 1 1 2.00 vhsub.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vhsub.s8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhsub.u8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhsub.s16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhsub.u16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhsub.s32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vhsub.u32 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 viwdup.u8 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 viwdup.u16 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 viwdup.u32 q0, r0, r1, #4
+# CHECK-NEXT: 1 4 2.00 vidup.u8 q0, r0, #4
+# CHECK-NEXT: 1 4 2.00 vidup.u16 q0, r0, #4
+# CHECK-NEXT: 1 4 2.00 vidup.u32 q0, r0, #4
+# CHECK-NEXT: 1 1 2.00 vmax.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmax.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmax.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmax.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmax.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmax.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmaxa.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vmaxa.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vmaxa.s32 q0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.u8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.s16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.u16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.s32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxv.u32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxav.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxav.s16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vmaxav.s32 r0, q2
+# CHECK-NEXT: 1 1 2.00 vmin.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmin.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmin.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmin.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmin.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmin.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmina.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vmina.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vmina.s32 q0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.u8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.s16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.u16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.s32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminv.u32 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminav.s8 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminav.s16 r0, q2
+# CHECK-NEXT: 1 4 2.00 vminav.s32 r0, q2
+# CHECK-NEXT: 1 2 2.00 vmla.i8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmla.i16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmla.i32 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vmlav.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlav.u8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlav.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlav.u16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlav.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlav.u32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.u8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.u16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlava.u32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavax.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavax.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavax.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavx.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavx.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmladavx.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalv.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalv.u16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalv.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalv.u32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalva.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalva.u16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalva.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlalva.u32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlaldavax.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlaldavax.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlaldavx.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlaldavx.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmlas.i8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmlas.i16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmlas.i32 q0, q2, r0
+# CHECK-NEXT: 1 4 2.00 vmlsdav.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdav.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdav.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdava.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdava.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdava.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavax.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavax.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavax.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavx.s8 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavx.s16 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsdavx.s32 r0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldav.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldav.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldava.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldava.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldavax.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldavax.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldavx.s16 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vmlsldavx.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 1 1.00 vmov.8 q0[1], r0
+# CHECK-NEXT: 1 1 1.00 vmov.16 q0[1], r0
+# CHECK-NEXT: 1 1 1.00 vmov.32 q0[1], r0
+# CHECK-NEXT: 1 1 1.00 vmov.i8 q0, #0x0
+# CHECK-NEXT: 1 1 1.00 vmov.i16 q0, #0x0
+# CHECK-NEXT: 1 1 1.00 vmov.i32 q0, #0x0
+# CHECK-NEXT: 1 1 1.00 vmov.i64 q0, #0x0
+# CHECK-NEXT: 1 1 1.00 vmov.f32 q0, #1.000000e+00
+# CHECK-NEXT: 1 4 1.00 vmov r1, r2, q0[2], q0[0]
+# CHECK-NEXT: 1 1 1.00 vmov q0[2], q0[0], r1, r2
+# CHECK-NEXT: 1 4 1.00 vmov.32 r0, q0[1]
+# CHECK-NEXT: 1 4 1.00 vmov.s16 r0, q0[1]
+# CHECK-NEXT: 1 4 1.00 vmov.u16 r0, q0[1]
+# CHECK-NEXT: 1 4 1.00 vmov.s8 r0, q0[1]
+# CHECK-NEXT: 1 4 1.00 vmov.u8 r0, q0[1]
+# CHECK-NEXT: 1 1 2.00 vmovlb.s8 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlb.u8 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlb.s16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlb.u16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlt.s8 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlt.u8 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlt.s16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovlt.u16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovnb.i16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovnb.i32 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovnt.i16 q0, q1
+# CHECK-NEXT: 1 1 2.00 vmovnt.i32 q0, q1
+# CHECK-NEXT: 1 2 2.00 vmul.i8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmul.i16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmul.i32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmul.i8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmul.i16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmul.i32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vmulh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmulh.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmulh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmulh.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmulh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmulh.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrmulh.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullb.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vmullt.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmullb.p8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmullb.p16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmullt.p8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vmullt.p16 q0, q2, q1
+# CHECK-NEXT: 1 1 1.00 vmvn.i16 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vmvn.i32 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vmvn q0, q2
+# CHECK-NEXT: 1 1 2.00 vneg.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vneg.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vneg.s32 q0, q2
+# CHECK-NEXT: 1 1 1.00 vorn q0, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorr.i16 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vorr.i32 q0, #0xa
+# CHECK-NEXT: 1 1 1.00 vorr q0, q2, q1
+# CHECK-NEXT: 1 1 1.00 vpsel q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqabs.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqabs.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqabs.s32 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqadd.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqadd.s8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqadd.u8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqadd.s16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqadd.u16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqadd.s32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqadd.u32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmladh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmladh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmladh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmladhx.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmladhx.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmladhx.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmladhx.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlah.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlah.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlah.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlah.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlah.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlah.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlash.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlash.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlash.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlash.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlash.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmlash.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlsdh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmlsdhx.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmlsdhx.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmulh.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s8 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqrdmulh.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmullt.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmullt.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqdmullb.s16 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqdmullb.s32 q0, q2, r0
+# CHECK-NEXT: 1 2 2.00 vqmovnt.s16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnt.u16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnt.s32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnt.u32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnb.s16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnb.u16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnb.s32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovnb.u32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovunt.s16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovunt.s32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovunb.s16 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqmovunb.s32 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqneg.s8 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqneg.s16 q0, q2
+# CHECK-NEXT: 1 1 2.00 vqneg.s32 q0, q2
+# CHECK-NEXT: 1 2 2.00 vqrshl.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqrshl.s8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshl.u8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshl.s16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshl.u16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshl.s32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshl.u32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqrshrnb.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnb.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnb.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnb.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnt.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnt.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnt.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrnt.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrunb.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrunb.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrunt.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqrshrunt.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshlu.s8 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshlu.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshlu.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshl.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshl.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshl.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshl.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshl.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshl.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vqshrnb.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnb.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnb.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnb.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnt.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnt.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnt.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrnt.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrunb.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrunb.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrunt.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vqshrunt.s32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vqsub.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.u32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vqsub.s8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqsub.u8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqsub.s16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqsub.u16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqsub.s32 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vqsub.u32 q0, q2, r0
+# CHECK-NEXT: 1 1 1.00 vrev16.8 q0, q2
+# CHECK-NEXT: 1 1 1.00 vrev32.8 q0, q2
+# CHECK-NEXT: 1 1 1.00 vrev32.16 q0, q2
+# CHECK-NEXT: 1 1 1.00 vrev64.8 q0, q2
+# CHECK-NEXT: 1 1 1.00 vrev64.16 q0, q2
+# CHECK-NEXT: 1 1 1.00 vrev64.32 q0, q2
+# CHECK-NEXT: 1 1 2.00 vrhadd.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vrhadd.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vrhadd.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vrhadd.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vrhadd.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vrhadd.u32 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlalvh.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlalvh.u32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlalvha.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlalvha.u32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlaldavhx.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlaldavhax.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlsldavh.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlsldavha.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlsldavhx.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 4 2.00 vrmlsldavhax.s32 r0, r1, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.s8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.u8 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.s16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.u16 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.s32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.u32 q0, q2, q1
+# CHECK-NEXT: 1 2 2.00 vrshl.s8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshl.u8 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshl.s16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshl.u16 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshl.s32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshl.u32 q0, r0
+# CHECK-NEXT: 1 2 2.00 vrshr.s8 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshr.u8 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshr.s16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshr.u16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshr.s32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshr.u32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshrnb.i16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshrnb.i32 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshrnt.i16 q0, q2, #5
+# CHECK-NEXT: 1 2 2.00 vrshrnt.i32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 U vsbc.i32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 U vsbci.i32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.i8 q0, q2, #1
+# CHECK-NEXT: 1 1 2.00 vshl.i16 q0, q2, #1
+# CHECK-NEXT: 1 1 2.00 vshl.i32 q0, q2, #1
+# CHECK-NEXT: 1 1 2.00 vshl.s8 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.u8 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.s16 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.u16 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.s32 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.u32 q0, r0
+# CHECK-NEXT: 1 1 2.00 vshl.s8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.u8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.s16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.u16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.s32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vshl.u32 q0, q2, q1
+# CHECK-NEXT: 1 4 2.00 U vshlc q0, r0, #5
+# CHECK-NEXT: 1 1 2.00 vshllt.s8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllt.u8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllt.s16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllt.u16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllb.s8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllb.u8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllb.s16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllb.u16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshllt.s8 q0, q2, #8
+# CHECK-NEXT: 1 1 2.00 vshllt.u8 q0, q2, #8
+# CHECK-NEXT: 1 1 2.00 vshllt.s16 q0, q2, #16
+# CHECK-NEXT: 1 1 2.00 vshllt.u16 q0, q2, #16
+# CHECK-NEXT: 1 1 2.00 vshllb.s8 q0, q2, #8
+# CHECK-NEXT: 1 1 2.00 vshllb.u8 q0, q2, #8
+# CHECK-NEXT: 1 1 2.00 vshllb.s16 q0, q2, #16
+# CHECK-NEXT: 1 1 2.00 vshllb.u16 q0, q2, #16
+# CHECK-NEXT: 1 1 2.00 vshr.s8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshr.u8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshr.s16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshr.u16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshr.s32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshr.u32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshrnb.i16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshrnb.i32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshrnt.i16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vshrnt.i32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsli.8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsli.16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsli.32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsri.8 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsri.16 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsri.32 q0, q2, #5
+# CHECK-NEXT: 1 1 2.00 vsub.i8 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vsub.i16 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vsub.i32 q0, q2, q1
+# CHECK-NEXT: 1 1 2.00 vsub.i8 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vsub.i16 q0, q2, r0
+# CHECK-NEXT: 1 1 2.00 vsub.i32 q0, q2, r0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M85UnitALU
+# CHECK-NEXT: [0.1] - M85UnitALU
+# CHECK-NEXT: [1] - M85UnitBranch
+# CHECK-NEXT: [2] - M85UnitDiv
+# CHECK-NEXT: [3] - M85UnitLShift
+# CHECK-NEXT: [4] - M85UnitLoadH
+# CHECK-NEXT: [5] - M85UnitLoadL
+# CHECK-NEXT: [6] - M85UnitMAC
+# CHECK-NEXT: [7] - M85UnitSIMD
+# CHECK-NEXT: [8] - M85UnitShift1
+# CHECK-NEXT: [9] - M85UnitShift2
+# CHECK-NEXT: [10] - M85UnitSlot0
+# CHECK-NEXT: [11] - M85UnitStoreH
+# CHECK-NEXT: [12] - M85UnitStoreL
+# CHECK-NEXT: [13] - M85UnitVFPAH
+# CHECK-NEXT: [14] - M85UnitVFPAL
+# CHECK-NEXT: [15] - M85UnitVFPBH
+# CHECK-NEXT: [16] - M85UnitVFPBL
+# CHECK-NEXT: [17] - M85UnitVFPCH
+# CHECK-NEXT: [18] - M85UnitVFPCL
+# CHECK-NEXT: [19] - M85UnitVFPD
+# CHECK-NEXT: [20] - M85UnitVPortH
+# CHECK-NEXT: [21] - M85UnitVPortL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
+# CHECK-NEXT: - - - - - - - - - - - 513.00 - - 630.00 630.00 316.00 316.00 - - - 513.00 513.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.u8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.u16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabav.u32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabd.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabs.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabs.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vabs.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadc.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadci.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vadd.i32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddlv.s32 r0, r1, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddlv.u32 r0, r1, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddlva.s32 r0, r1, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddlva.u32 r0, r1, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.s8 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.u8 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.s16 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.u16 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.s32 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vaddv.u32 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.s8 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.u8 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.s16 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.u16 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.s32 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vaddva.u32 r0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vand q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vbic.i16 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vbic.i32 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vbic q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vbrsr.8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vbrsr.16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vbrsr.32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vcadd.i8 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vcadd.i16 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vcadd.i32 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vcls.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vcls.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vcls.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vclz.i8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vclz.i16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vclz.i32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdwdup.u8 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdwdup.u16 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdwdup.u32 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vddup.u8 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vddup.u16 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vddup.u32 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdup.8 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdup.16 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vdup.32 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 veor q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.s32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhadd.u32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhcadd.s8 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhcadd.s16 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhcadd.s32 q0, q2, q1, #90
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.s32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vhsub.u32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 viwdup.u8 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 viwdup.u16 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 viwdup.u32 q0, r0, r1, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vidup.u8 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vidup.u16 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vidup.u32 q0, r0, #4
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmax.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxa.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxa.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxa.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.s8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.u8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.s16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.u16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.s32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxv.u32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxav.s8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxav.s16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmaxav.s32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmin.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmina.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmina.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmina.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.s8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.u8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.s16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.u16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.s32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminv.u32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminav.s8 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminav.s16 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vminav.s32 r0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmla.i8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmla.i16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmla.i32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.u8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.u16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlav.u32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.u8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.u16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlava.u32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavax.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavax.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavax.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavx.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavx.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmladavx.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalv.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalv.u16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalv.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalv.u32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalva.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalva.u16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalva.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlalva.u32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlaldavax.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlaldavax.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlaldavx.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlaldavx.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlas.i8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlas.i16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlas.i32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdav.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdav.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdav.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdava.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdava.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdava.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavax.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavax.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavax.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavx.s8 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavx.s16 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsdavx.s32 r0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldav.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldav.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldava.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldava.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldavax.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldavax.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldavx.s16 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmlsldavx.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.8 q0[1], r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.16 q0[1], r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.32 q0[1], r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.i8 q0, #0x0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.i16 q0, #0x0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.i32 q0, #0x0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.i64 q0, #0x0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.f32 q0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov r1, r2, q0[2], q0[0]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov q0[2], q0[0], r1, r2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.32 r0, q0[1]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.s16 r0, q0[1]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.u16 r0, q0[1]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.s8 r0, q0[1]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmov.u8 r0, q0[1]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlb.s8 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlb.u8 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlb.s16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlb.u16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlt.s8 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlt.u8 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlt.s16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovlt.u16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovnb.i16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovnb.i32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovnt.i16 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmovnt.i32 q0, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmul.i32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmulh.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmulh.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullb.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vmullt.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmullb.p8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmullb.p16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmullt.p8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vmullt.p16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmvn.i16 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmvn.i32 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vmvn q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vneg.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vneg.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vneg.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorn q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorr.i16 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorr.i32 q0, #0xa
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorr q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vpsel q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqabs.s8 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqabs.s16 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqabs.s32 q0, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.s32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vqadd.u32 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladh.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladh.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladh.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladhx.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladhx.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqdmladhx.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqrdmladh.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqrdmladh.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqrdmladh.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vqrdmladhx.s8 q0, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmlaldavhax.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmlsldavh.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmlsldavha.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmlsldavhx.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - 2.00 2.00 - - - 1.00 1.00 vrmlsldavhax.s32 r0, r1, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s8 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u8 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s16 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u16 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.s32 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshl.u32 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.s8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.u8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.s16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.u16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.s32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshr.u32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshrnb.i16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshrnb.i32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshrnt.i16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vrshrnt.i32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsbc.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsbci.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.i8 q0, q2, #1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.i16 q0, q2, #1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.i32 q0, q2, #1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s8 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u8 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s16 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u16 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s32 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u32 q0, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.s32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshl.u32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshlc q0, r0, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.s8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.u8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.s16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.u16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.s8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.u8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.s16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.u16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.s8 q0, q2, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.u8 q0, q2, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.s16 q0, q2, #16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllt.u16 q0, q2, #16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.s8 q0, q2, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.u8 q0, q2, #8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.s16 q0, q2, #16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshllb.u16 q0, q2, #16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.s8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.u8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.s16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.u16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.s32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshr.u32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshrnb.i16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshrnb.i32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshrnt.i16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vshrnt.i32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsli.8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsli.16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsli.32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsri.8 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsri.16 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsri.32 q0, q2, #5
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i8 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i16 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i32 q0, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i8 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i16 q0, q2, r0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - 2.00 2.00 - - - - - 1.00 1.00 vsub.i32 q0, q2, r0
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s
new file mode 100644
index 00000000000000..5e787a410e32ab
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s
@@ -0,0 +1,724 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s
+
+vcmp.f16 eq, q2, q1
+vcmp.f32 eq, q2, q1
+vcmp.f16 ne, q2, q1
+vcmp.f32 ne, q2, q1
+vcmp.f16 ge, q2, q1
+vcmp.f32 ge, q2, q1
+vcmp.f16 lt, q2, q1
+vcmp.f32 lt, q2, q1
+vcmp.f16 gt, q2, q1
+vcmp.f32 gt, q2, q1
+vcmp.f16 le, q2, q1
+vcmp.f32 le, q2, q1
+vcmp.f16 eq, q2, r1
+vcmp.f32 eq, q2, r1
+vcmp.f16 ne, q2, r1
+vcmp.f32 ne, q2, r1
+vcmp.f16 ge, q2, r1
+vcmp.f32 ge, q2, r1
+vcmp.f16 lt, q2, r1
+vcmp.f32 lt, q2, r1
+vcmp.f16 gt, q2, r1
+vcmp.f32 gt, q2, r1
+vcmp.f16 le, q2, r1
+vcmp.f32 le, q2, r1
+vcmp.i8 eq, q2, q1
+vcmp.i16 eq, q2, q1
+vcmp.i32 eq, q2, q1
+vcmp.i8 ne, q2, q1
+vcmp.i16 ne, q2, q1
+vcmp.i32 ne, q2, q1
+vcmp.u8 cs, q2, q1
+vcmp.u16 cs, q2, q1
+vcmp.u32 cs, q2, q1
+vcmp.u8 hi, q2, q1
+vcmp.u16 hi, q2, q1
+vcmp.u32 hi, q2, q1
+vcmp.s8 ge, q2, q1
+vcmp.s16 ge, q2, q1
+vcmp.s32 ge, q2, q1
+vcmp.s8 lt, q2, q1
+vcmp.s16 lt, q2, q1
+vcmp.s32 lt, q2, q1
+vcmp.s8 gt, q2, q1
+vcmp.s16 gt, q2, q1
+vcmp.s32 gt, q2, q1
+vcmp.s8 le, q2, q1
+vcmp.s16 le, q2, q1
+vcmp.s32 le, q2, q1
+vcmp.i8 eq, q2, r1
+vcmp.i16 eq, q2, r1
+vcmp.i32 eq, q2, r1
+vcmp.i8 ne, q2, r1
+vcmp.i16 ne, q2, r1
+vcmp.i32 ne, q2, r1
+vcmp.u8 cs, q2, r1
+vcmp.u16 cs, q2, r1
+vcmp.u32 cs, q2, r1
+vcmp.u8 hi, q2, r1
+vcmp.u16 hi, q2, r1
+vcmp.u32 hi, q2, r1
+vcmp.s8 ge, q2, r1
+vcmp.s16 ge, q2, r1
+vcmp.s32 ge, q2, r1
+vcmp.s8 lt, q2, r1
+vcmp.s16 lt, q2, r1
+vcmp.s32 lt, q2, r1
+vcmp.s8 gt, q2, r1
+vcmp.s16 gt, q2, r1
+vcmp.s32 gt, q2, r1
+vcmp.s8 le, q2, r1
+vcmp.s16 le, q2, r1
+vcmp.s32 le, q2, r1
+vctp.8 r0
+vctp.16 r0
+vctp.32 r0
+vctp.64 r0
+#vpnot FIXME: crashes compiler
+vpst
+vorrt q0, q0, q0
+vpt.f16 eq, q2, q1
+vorrt q0, q1, q2
+vpt.f32 eq, q2, q1
+vorrt q0, q1, q2
+vpt.f16 ne, q2, q1
+vorrt q0, q1, q2
+vpt.f32 ne, q2, q1
+vorrt q0, q1, q2
+vpt.f16 ge, q2, q1
+vorrt q0, q1, q2
+vpt.f32 ge, q2, q1
+vorrt q0, q1, q2
+vpt.f16 lt, q2, q1
+vorrt q0, q1, q2
+vpt.f32 lt, q2, q1
+vorrt q0, q1, q2
+vpt.f16 gt, q2, q1
+vorrt q0, q1, q2
+vpt.f32 gt, q2, q1
+vorrt q0, q1, q2
+vpt.f16 le, q2, q1
+vorrt q0, q1, q2
+vpt.f32 le, q2, q1
+vorrt q0, q1, q2
+vpt.f16 eq, q2, r1
+vorrt q0, q1, q2
+vpt.f32 eq, q2, r1
+vorrt q0, q1, q2
+vpt.f16 ne, q2, r1
+vorrt q0, q1, q2
+vpt.f32 ne, q2, r1
+vorrt q0, q1, q2
+vpt.f16 ge, q2, r1
+vorrt q0, q1, q2
+vpt.f32 ge, q2, r1
+vorrt q0, q1, q2
+vpt.f16 lt, q2, r1
+vorrt q0, q1, q2
+vpt.f32 lt, q2, r1
+vorrt q0, q1, q2
+vpt.f16 gt, q2, r1
+vorrt q0, q1, q2
+vpt.f32 gt, q2, r1
+vorrt q0, q1, q2
+vpt.f16 le, q2, r1
+vorrt q0, q1, q2
+vpt.f32 le, q2, r1
+vorrt q0, q1, q2
+vpt.i8 eq, q2, q1
+vorrt q0, q1, q2
+vpt.i16 eq, q2, q1
+vorrt q0, q1, q2
+vpt.i32 eq, q2, q1
+vorrt q0, q1, q2
+vpt.i8 ne, q2, q1
+vorrt q0, q1, q2
+vpt.i16 ne, q2, q1
+vorrt q0, q1, q2
+vpt.i32 ne, q2, q1
+vorrt q0, q1, q2
+vpt.u8 cs, q2, q1
+vorrt q0, q1, q2
+vpt.u16 cs, q2, q1
+vorrt q0, q1, q2
+vpt.u32 cs, q2, q1
+vorrt q0, q1, q2
+vpt.u8 hi, q2, q1
+vorrt q0, q1, q2
+vpt.u16 hi, q2, q1
+vorrt q0, q1, q2
+vpt.u32 hi, q2, q1
+vorrt q0, q1, q2
+vpt.s8 ge, q2, q1
+vorrt q0, q1, q2
+vpt.s16 ge, q2, q1
+vorrt q0, q1, q2
+vpt.s32 ge, q2, q1
+vorrt q0, q1, q2
+vpt.s8 lt, q2, q1
+vorrt q0, q1, q2
+vpt.s16 lt, q2, q1
+vorrt q0, q1, q2
+vpt.s32 lt, q2, q1
+vorrt q0, q1, q2
+vpt.s8 gt, q2, q1
+vorrt q0, q1, q2
+vpt.s16 gt, q2, q1
+vorrt q0, q1, q2
+vpt.s32 gt, q2, q1
+vorrt q0, q1, q2
+vpt.s8 le, q2, q1
+vorrt q0, q1, q2
+vpt.s16 le, q2, q1
+vorrt q0, q1, q2
+vpt.s32 le, q2, q1
+vorrt q0, q1, q2
+vpt.i8 eq, q2, r1
+vorrt q0, q1, q2
+vpt.i16 eq, q2, r1
+vorrt q0, q1, q2
+vpt.i32 eq, q2, r1
+vorrt q0, q1, q2
+vpt.i8 ne, q2, r1
+vorrt q0, q1, q2
+vpt.i16 ne, q2, r1
+vorrt q0, q1, q2
+vpt.i32 ne, q2, r1
+vorrt q0, q1, q2
+vpt.u8 cs, q2, r1
+vorrt q0, q1, q2
+vpt.u16 cs, q2, r1
+vorrt q0, q1, q2
+vpt.u32 cs, q2, r1
+vorrt q0, q1, q2
+vpt.u8 hi, q2, r1
+vorrt q0, q1, q2
+vpt.u16 hi, q2, r1
+vorrt q0, q1, q2
+vpt.u32 hi, q2, r1
+vorrt q0, q1, q2
+vpt.s8 ge, q2, r1
+vorrt q0, q1, q2
+vpt.s16 ge, q2, r1
+vorrt q0, q1, q2
+vpt.s32 ge, q2, r1
+vorrt q0, q1, q2
+vpt.s8 lt, q2, r1
+vorrt q0, q1, q2
+vpt.s16 lt, q2, r1
+vorrt q0, q1, q2
+vpt.s32 lt, q2, r1
+vorrt q0, q1, q2
+vpt.s8 gt, q2, r1
+vorrt q0, q1, q2
+vpt.s16 gt, q2, r1
+vorrt q0, q1, q2
+vpt.s32 gt, q2, r1
+vorrt q0, q1, q2
+vpt.s8 le, q2, r1
+vorrt q0, q1, q2
+vpt.s16 le, q2, r1
+vorrt q0, q1, q2
+vpt.s32 le, q2, r1
+vorrt q0, q1, q2
+vstr p0, [r1]
+vldr p0, [r2]
+vpst
+vorrt q0, q1, q2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 eq, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 eq, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 ne, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 ne, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 ge, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 ge, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 lt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 lt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 gt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 gt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 le, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 le, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 eq, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 eq, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 ne, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 ne, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 ge, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 ge, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 lt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 lt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 gt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 gt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f16 le, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.f32 le, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i8 eq, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i16 eq, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i32 eq, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i8 ne, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i16 ne, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i32 ne, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u8 cs, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u16 cs, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u32 cs, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u8 hi, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u16 hi, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.u32 hi, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 ge, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 ge, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 ge, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 lt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 lt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 lt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 gt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 gt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 gt, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 le, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 le, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 le, q2, q1
+# CHECK-NEXT: 1 1 2.00 vcmp.i8 eq, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i16 eq, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i32 eq, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i8 ne, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i16 ne, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.i32 ne, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u8 cs, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u16 cs, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u32 cs, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u8 hi, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u16 hi, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.u32 hi, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 ge, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 ge, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 ge, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 lt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 lt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 lt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 gt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 gt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 gt, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s8 le, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s16 le, q2, r1
+# CHECK-NEXT: 1 1 2.00 vcmp.s32 le, q2, r1
+# CHECK-NEXT: 1 1 2.00 vctp.8 r0
+# CHECK-NEXT: 1 1 2.00 vctp.16 r0
+# CHECK-NEXT: 1 1 2.00 vctp.32 r0
+# CHECK-NEXT: 1 1 2.00 vctp.64 r0
+# CHECK-NEXT: 1 1 2.00 U vpst
+# CHECK-NEXT: 1 1 1.00 vmovt q0, q0
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 eq, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 eq, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 ne, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 ne, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 ge, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 ge, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 lt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 lt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 gt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 gt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 le, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 le, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 eq, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 eq, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 ne, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 ne, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 ge, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 ge, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 lt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 lt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 gt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 gt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f16 le, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.f32 le, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i8 eq, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i16 eq, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i32 eq, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i8 ne, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i16 ne, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i32 ne, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u8 cs, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u16 cs, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u32 cs, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u8 hi, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u16 hi, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u32 hi, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 ge, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 ge, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 ge, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 lt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 lt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 lt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 gt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 gt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 gt, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 le, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 le, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 le, q2, q1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i8 eq, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i16 eq, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i32 eq, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i8 ne, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i16 ne, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.i32 ne, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u8 cs, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u16 cs, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u32 cs, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u8 hi, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u16 hi, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.u32 hi, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 ge, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 ge, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 ge, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 lt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 lt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 lt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 gt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 gt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 gt, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s8 le, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s16 le, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 1 2.00 U vpt.s32 le, q2, r1
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: 1 2 1.00 * U vstr p0, [r1]
+# CHECK-NEXT: 1 5 1.00 * U vldr p0, [r2]
+# CHECK-NEXT: 1 1 2.00 U vpst
+# CHECK-NEXT: 1 1 1.00 vorrt q0, q1, q2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M85UnitALU
+# CHECK-NEXT: [0.1] - M85UnitALU
+# CHECK-NEXT: [1] - M85UnitBranch
+# CHECK-NEXT: [2] - M85UnitDiv
+# CHECK-NEXT: [3] - M85UnitLShift
+# CHECK-NEXT: [4] - M85UnitLoadH
+# CHECK-NEXT: [5] - M85UnitLoadL
+# CHECK-NEXT: [6] - M85UnitMAC
+# CHECK-NEXT: [7] - M85UnitSIMD
+# CHECK-NEXT: [8] - M85UnitShift1
+# CHECK-NEXT: [9] - M85UnitShift2
+# CHECK-NEXT: [10] - M85UnitSlot0
+# CHECK-NEXT: [11] - M85UnitStoreH
+# CHECK-NEXT: [12] - M85UnitStoreL
+# CHECK-NEXT: [13] - M85UnitVFPAH
+# CHECK-NEXT: [14] - M85UnitVFPAL
+# CHECK-NEXT: [15] - M85UnitVFPBH
+# CHECK-NEXT: [16] - M85UnitVFPBL
+# CHECK-NEXT: [17] - M85UnitVFPCH
+# CHECK-NEXT: [18] - M85UnitVFPCL
+# CHECK-NEXT: [19] - M85UnitVFPD
+# CHECK-NEXT: [20] - M85UnitVPortH
+# CHECK-NEXT: [21] - M85UnitVPortL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 224.00 0.50 0.50 1.00 1.00 1.00 1.00 289.00 289.00 14.00 225.00 225.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 eq, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 eq, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 ne, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 ne, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 ge, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 ge, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 lt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 lt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 le, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 le, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 eq, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 eq, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 ne, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 ne, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 gt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 gt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f16 le, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.f32 le, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i8 eq, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i16 eq, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i32 eq, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i8 ne, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i16 ne, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i32 ne, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u8 cs, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u16 cs, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u32 cs, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u8 hi, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u16 hi, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u32 hi, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s8 ge, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s16 ge, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 ge, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s16 lt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 lt, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s16 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 gt, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i8 ne, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i16 ne, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.i32 ne, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u16 cs, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u32 cs, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.u8 hi, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s8 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s16 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s8 lt, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s8 gt, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vcmp.s32 gt, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.u32 cs, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 ge, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 ge, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 lt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 lt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 gt, q2, q1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 le, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 le, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 le, q2, q1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.u32 cs, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.u8 hi, q2, r1
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+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.u16 hi, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.u32 hi, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 ge, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 lt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 gt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 gt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 gt, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s8 le, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s16 le, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - 2.00 2.00 - 1.00 1.00 vpt.s32 le, q2, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 1.00 0.50 0.50 vstr p0, [r1]
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - 0.50 0.50 0.50 0.50 0.50 0.50 1.00 0.50 0.50 vldr p0, [r2]
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - 2.00 1.00 1.00 vpst
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - 1.00 1.00 vorrt q0, q1, q2
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