[PATCH] D158596: [GlobalISel] Limit shift_of_shifted_logic_chain to non-zero folds

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
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After D157690 <https://reviews.llvm.org/D157690> we are seeing some crashes from Global ISel, which seem to be related to the shift_of_shifted_logic_chain combine that can remove too many instructions if the shift amount is zero. See https://godbolt.org/z/8Y4vd81TT.

This limits the fold to non-zero shifts, under the assumption that it is better then to fold the shift to a COPY.


https://reviews.llvm.org/D158596

Files:
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
@@ -433,3 +433,29 @@
     RET_ReallyLR
 
 ...
+---
+name:            mul_1_shift_of_shift
+liveins:
+  - { reg: '$x0' }
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: mul_1_shift_of_shift
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[C]]
+    ; CHECK-NEXT: $x0 = COPY [[OR]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = G_CONSTANT i64 1
+    %2:_(s64) = G_SHL %0, %1(s64)
+    %3:_(s64) = G_OR %2, %1
+    %4:_(s64) = G_MUL %3, %1
+    $x0 = COPY %4(s64)
+    RET_ReallyLR implicit $x0
+
+...
Index: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1535,7 +1535,7 @@
   // Find a matching one-use shift by constant.
   const Register C1 = MI.getOperand(2).getReg();
   auto MaybeImmVal = getIConstantVRegValWithLookThrough(C1, MRI);
-  if (!MaybeImmVal)
+  if (!MaybeImmVal || MaybeImmVal->Value == 0)
     return false;
 
   const uint64_t C1Val = MaybeImmVal->Value.getZExtValue();


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