[PATCH] D158460: [RISCV] Reduce LMUL for vector extracts

[Philip Reames via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGecb855a5a8c5: [RISCV] Reduce LMUL for vector extracts (authored by reames).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158460/new/

https://reviews.llvm.org/D158460

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

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