[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc marked an inline comment as done.
wangpc added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:379
   }
-
+  NonLibcallCSI.insert(IsRestore ? NonLibcallCSI.begin() : NonLibcallCSI.end(),
+                       CSRs.begin(), CSRs.end());
----------------
Jim wrote:
> If we put FCSR at first in CSR_XLEN_F32_Interrupt/CSR_XLEN_F64_Interrupt, is it still need to depend on save or restore to determinate the order of CSR inserted.
Yes. We should save FCSR after saving `t0` and restore it before restoring `t0` since we are using `t0` as a temporary register.


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  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492