[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:379
   }
-
+  NonLibcallCSI.insert(IsRestore ? NonLibcallCSI.begin() : NonLibcallCSI.end(),
+                       CSRs.begin(), CSRs.end());
----------------
If we put FCSR at first in CSR_XLEN_F32_Interrupt/CSR_XLEN_F64_Interrupt, is it still need to depend on save or restore to determinate the order of CSR inserted.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:577
   // register.
-  std::advance(MBBI, getUnmanagedCSI(MF, CSI).size());
+  std::advance(MBBI, getUnmanagedCSI(MF, CSI, /*IsRetore*/ false).size());
 
----------------
Typo. IsRestore.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492