[PATCH] D158492: [RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc updated this revision to Diff 552256.
wangpc added a comment.

Fix wrong restore dst reg.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158492/new/

https://reviews.llvm.org/D158492

Files:
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
  llvm/test/CodeGen/RISCV/interrupt-attr.ll

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