[PATCH] D158460: [RISCV] Reduce LMUL for vector extracts

[Philip Reames via Phabricator via llvm-commits]

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If we have a known (or bounded) index which definitely fits in a smaller LMUL register group size, we can reduce the LMUL of the slide and extract instructions.  This loosens constraints on register allocation, and allows the hardware to do less work, at the potential cost of some additional VTYPE toggles.  In practice, we appear (after prior patches) to do a decent job of eliminating the additional VTYPE toggles in most cases.

A couple of side notes:

1. I stopped at m1 here.  For machines with a DLEN < VLEN, we should probably be doing mf2, but we need to make that change a bit more globally as well.
2. Arguably, we should be narrowing the LMUL of *most* operations which are provably don't care in their input and outputs.  We've got a few selected cases, but maybe it's time to generalize something more general?  (Definitely future work!)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158460

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

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