[PATCH] D158392: [RISCV] Fix `vmsge{u}.vx` lowering by not adding the mask operand if `vd == v0`
Kiva Oyama via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 21 00:44:55 PDT 2023
imkiva updated this revision to Diff 551917.
imkiva added a comment.
Reformat some comments so they look nicer.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158392/new/
https://reviews.llvm.org/D158392
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/test/MC/RISCV/rvv/compare.s
Index: llvm/test/MC/RISCV/rvv/compare.s
===================================================================
--- llvm/test/MC/RISCV/rvv/compare.s
+++ llvm/test/MC/RISCV/rvv/compare.s
@@ -420,21 +420,21 @@
# CHECK-UNKNOWN: 57 24 80 6e <unknown>
vmsgeu.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmsltu.vx v2, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v2, v4, a0
# CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x68]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6a]
# CHECK-ENCODING: [0x57,0x20,0x01,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 68 <unknown>
+# CHECK-UNKNOWN: 57 41 45 6a <unknown>
# CHECK-UNKNOWN: 57 20 01 62 <unknown>
vmsge.vx v0, v4, a0, v0.t, v2
-# CHECK-INST: vmslt.vx v2, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v2, v4, a0
# CHECK-INST: vmandn.mm v0, v0, v2
-# CHECK-ENCODING: [0x57,0x41,0x45,0x6c]
+# CHECK-ENCODING: [0x57,0x41,0x45,0x6e]
# CHECK-ENCODING: [0x57,0x20,0x01,0x62]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
-# CHECK-UNKNOWN: 57 41 45 6c <unknown>
+# CHECK-UNKNOWN: 57 41 45 6e <unknown>
# CHECK-UNKNOWN: 57 20 01 62 <unknown>
vmsgeu.vx v9, v4, a0, v0.t, v2
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3203,7 +3203,7 @@
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
.addOperand(Inst.getOperand(3))
- .addOperand(Inst.getOperand(4)));
+ .addReg(RISCV::NoRegister));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(0))
@@ -3212,8 +3212,8 @@
// masked va >= x, any vd
//
// pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
- // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd,
- // vd, v0; vmor.mm vd, vt, vd
+ // expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt;
+ // vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd
assert(Inst.getOperand(1).getReg() != RISCV::V0 &&
"The temporary vector register should not be V0.");
emitToStreamer(Out, MCInstBuilder(Opcode)
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D158392.551917.patch
Type: text/x-patch
Size: 2669 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230821/76068b99/attachment.bin>
More information about the llvm-commits
mailing list