[llvm] 01da5b9 - [RISCV] Remove trailing whitespace. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 20 19:01:56 PDT 2023
Author: Jim Lin
Date: 2023-08-21T10:01:13+08:00
New Revision: 01da5b9438a9df40756e2176cffa1cb88f56dc60
URL: https://github.com/llvm/llvm-project/commit/01da5b9438a9df40756e2176cffa1cb88f56dc60
DIFF: https://github.com/llvm/llvm-project/commit/01da5b9438a9df40756e2176cffa1cb88f56dc60.diff
LOG: [RISCV] Remove trailing whitespace. NFC.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index d0d0e32334484b..353a4c7bde2ff6 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -107,8 +107,8 @@ bool RISCVExpandAtomicPseudo::expandMBB(MachineBasicBlock &MBB) {
bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) {
- // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
- // expanded instructions for each pseudo is correct in the Size field of the
+ // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
+ // expanded instructions for each pseudo is correct in the Size field of the
// tablegen definition for the pseudo.
switch (MBBI->getOpcode()) {
case RISCV::PseudoAtomicLoadNand32:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 2044c663b62f4d..582fe60fd0368e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1921,7 +1921,7 @@ def : Pat<(debugtrap), (EBREAK)>;
let Predicates = [IsRV64], Uses = [X5],
Defs = [X1, X6, X7, X28, X29, X30, X31] in
-def HWASAN_CHECK_MEMACCESS_SHORTGRANULES
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES
: Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
[(int_hwasan_check_memaccess_shortgranules (i64 X5), GPRJALR:$ptr,
(i32 timm:$accessinfo))]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 483da01276de3b..935a5f22d3ea98 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -31,7 +31,7 @@
/// the exact bit pattern of inactive lanes, or produce the bit pattern -1 for
/// those lanes. Note that each lane can make this choice independently.
/// Instructions which produce masks (and only those instructions) also have the
-/// option of producing a result as-if VL had been VLMAX.
+/// option of producing a result as-if VL had been VLMAX.
/// * "Undefined" - The bit pattern of the inactive lanes is unspecified, and
/// can be changed without impacting the semantics of the program. Note that
/// this concept does not exist in the specification, and requires source
@@ -68,7 +68,7 @@
/// confusing. We're in the process of migrating away from this
/// representation.
/// * _TU w/o policy operand -- Has a passthrough operand, and always
-/// represents the tail undisturbed state.
+/// represents the tail undisturbed state.
/// * _TU w/policy operand - Can represent all three policy states. If
/// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".
/// Otherwise, policy operand and tablegen flags drive the interpretation.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 20334ad8e4859a..fb0960011f5df7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1058,13 +1058,13 @@ foreach vtiTowti = AllWidenableIntVectors in {
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
def : Pat<
- (vti.Vector
+ (vti.Vector
(riscv_trunc_vector_vl
(srem (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs2)))),
(vti.Mask true_mask), (XLenVT srcvalue))),
(!cast<Instruction>("PseudoVREM_VV_"#vti.LMul.MX#"_E"#!shl(1, vti.Log2SEW))
- (vti.Vector (IMPLICIT_DEF)),
+ (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 505f8d3edc2df2..1a6145f9290813 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -487,22 +487,22 @@ defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
vbool32_t, vbool64_t];
defvar VM1VTs = [vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
- vbfloat16m1_t, vfloat16m1_t, vfloat32m1_t,
+ vbfloat16m1_t, vfloat16m1_t, vfloat32m1_t,
vfloat64m1_t, vint8mf2_t, vint8mf4_t, vint8mf8_t,
vint16mf2_t, vint16mf4_t, vint32mf2_t,
- vfloat16mf4_t, vfloat16mf2_t, vbfloat16mf4_t,
+ vfloat16mf4_t, vfloat16mf2_t, vbfloat16mf4_t,
vbfloat16mf2_t, vfloat32mf2_t];
defvar VM2VTs = [vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
- vfloat16m2_t, vbfloat16m2_t,
+ vfloat16m2_t, vbfloat16m2_t,
vfloat32m2_t, vfloat64m2_t];
-
+
defvar VM4VTs = [vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
- vfloat16m4_t, vbfloat16m4_t,
+ vfloat16m4_t, vbfloat16m4_t,
vfloat32m4_t, vfloat64m4_t];
-
+
defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
- vfloat16m8_t, vbfloat16m8_t,
+ vfloat16m8_t, vbfloat16m8_t,
vfloat32m8_t, vfloat64m8_t];
def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
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