[PATCH] D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 551866.
craig.topper added a comment.

Use the size of the GPR register bank to determine RV32 vs RV64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76051/new/

https://reviews.llvm.org/D76051

Files:
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir

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