[llvm] 95865e5 - [DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-20T14:20:49+01:00
New Revision: 95865e5138e2b69e371c334bbe945f673c30b24f

URL: https://github.com/llvm/llvm-project/commit/95865e5138e2b69e371c334bbe945f673c30b24f
DIFF: https://github.com/llvm/llvm-project/commit/95865e5138e2b69e371c334bbe945f673c30b24f.diff

LOG: [DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

Alive2: https://alive2.llvm.org/ce/z/MehvFB

REAPPLIED from 54d663d5896008 with fix for using the correct DemandedBits mask.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/X86/combine-smax.ll
    llvm/test/CodeGen/X86/combine-smin.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 4eb48e65df6084..fa07dba142f8c6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2135,6 +2135,24 @@ bool TargetLowering::SimplifyDemandedBits(
     }
     break;
   }
+  case ISD::SMIN: {
+    SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the signbit, then we can simplify to OR node.
+    // TODO: Extend this based on ComputeNumSignBits.
+    if (DemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
+    break;
+  }
+  case ISD::SMAX: {
+    SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the signbit, then we can simplify to AND node.
+    // TODO: Extend this based on ComputeNumSignBits.
+    if (DemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));
+    break;
+  }
   case ISD::UMIN: {
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);

diff  --git a/llvm/test/CodeGen/X86/combine-smax.ll b/llvm/test/CodeGen/X86/combine-smax.ll
index 39c2f4dcd95db0..aefa36d8c371b9 100644
--- a/llvm/test/CodeGen/X86/combine-smax.ll
+++ b/llvm/test/CodeGen/X86/combine-smax.ll
@@ -105,27 +105,27 @@ define <16 x i8> @test_v16i8_demandedbits(<16 x i8> %x, <16 x i8> %y, <16 x i8>
 ;
 ; SSE41-LABEL: test_v16i8_demandedbits:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
+; SSE41-NEXT:    andps %xmm1, %xmm0
 ; SSE41-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; SSE42-LABEL: test_v16i8_demandedbits:
 ; SSE42:       # %bb.0:
-; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
+; SSE42-NEXT:    andps %xmm1, %xmm0
 ; SSE42-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
 ; SSE42-NEXT:    movdqa %xmm2, %xmm0
 ; SSE42-NEXT:    retq
 ;
 ; AVX1OR2-LABEL: test_v16i8_demandedbits:
 ; AVX1OR2:       # %bb.0:
-; AVX1OR2-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX1OR2-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; AVX1OR2-NEXT:    vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
 ; AVX1OR2-NEXT:    retq
 ;
 ; AVX512F-LABEL: test_v16i8_demandedbits:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; AVX512F-NEXT:    vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
 ; AVX512F-NEXT:    retq
 ;

diff  --git a/llvm/test/CodeGen/X86/combine-smin.ll b/llvm/test/CodeGen/X86/combine-smin.ll
index 357e1060fc2b1d..cd3d74f65fe48b 100644
--- a/llvm/test/CodeGen/X86/combine-smin.ll
+++ b/llvm/test/CodeGen/X86/combine-smin.ll
@@ -107,27 +107,27 @@ define <16 x i8> @test_v16i8_demandedbits(<16 x i8> %x, <16 x i8> %y, <16 x i8>
 ;
 ; SSE41-LABEL: test_v16i8_demandedbits:
 ; SSE41:       # %bb.0:
-; SSE41-NEXT:    pminsb %xmm1, %xmm0
+; SSE41-NEXT:    orps %xmm1, %xmm0
 ; SSE41-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
 ; SSE41-NEXT:    movdqa %xmm2, %xmm0
 ; SSE41-NEXT:    retq
 ;
 ; SSE42-LABEL: test_v16i8_demandedbits:
 ; SSE42:       # %bb.0:
-; SSE42-NEXT:    pminsb %xmm1, %xmm0
+; SSE42-NEXT:    orps %xmm1, %xmm0
 ; SSE42-NEXT:    pblendvb %xmm0, %xmm3, %xmm2
 ; SSE42-NEXT:    movdqa %xmm2, %xmm0
 ; SSE42-NEXT:    retq
 ;
 ; AVX1OR2-LABEL: test_v16i8_demandedbits:
 ; AVX1OR2:       # %bb.0:
-; AVX1OR2-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
+; AVX1OR2-NEXT:    vpor %xmm1, %xmm0, %xmm0
 ; AVX1OR2-NEXT:    vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
 ; AVX1OR2-NEXT:    retq
 ;
 ; AVX512F-LABEL: test_v16i8_demandedbits:
 ; AVX512F:       # %bb.0:
-; AVX512F-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT:    vpor %xmm1, %xmm0, %xmm0
 ; AVX512F-NEXT:    vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
 ; AVX512F-NEXT:    retq
 ;