[PATCH] D158324: Revert "[RegisterCoalescing] Don't move COPY if it would interfere with another value"

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 18 16:10:27 PDT 2023


arsenm created this revision.
arsenm added reviewers: uabelho, wmi, qcolombet, MatzeB, sdardis.
Herald added subscribers: tpr, atanasyan, jrtc27, hiraditya.
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arsenm requested review of this revision.
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This reverts commit 6c062b7641623b1cfd2f359edb3118a4810c965e.

      

The testcase was invalid and failed the verifier after LiveIntervals
construction. I am unable to see the original error when I correct the
value numbering.


https://reviews.llvm.org/D158324

Files:
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir


Index: llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
===================================================================
--- llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
+++ llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
@@ -1,38 +1,32 @@
-# RUN: llc -march=mips64 -o - %s -run-pass=register-coalescer | FileCheck %s
+# RUN: llc -march=mips64 -o - %s -run-pass=register-coalescer -verify-coalescing | FileCheck %s
 
 ---
 name:            f
 tracksRegLiveness: true
 body:             |
- bb.0:
-    successors: %bb.1
-
-    %21:gpr32 = ADDiu $zero, 0
-    %22:gpr32 = COPY %21
-    %22:gpr32 = ADDiu %22, 1
+  bb.0:
+    %0:gpr32 = ADDiu $zero, 0
+    %1:gpr32 = COPY %0
+    %2:gpr32 = ADDiu %1, 1
     J %bb.1, implicit-def dead $at
 
- bb.1:
-    successors: %bb.2
-
-    BEQ %22, $zero, %bb.2, implicit-def $at
-
- bb.2:
-    successors: %bb.2, %bb.3
+  bb.1:
+    BEQ %2, $zero, %bb.2, implicit-def $at
 
-    %22:gpr32 = COPY %21
-    %21:gpr32 = COPY %22
-    BEQ undef %0:gpr32, $zero, %bb.2, implicit-def $at
+  bb.2:
+    %3:gpr32 = COPY %0
+    %0:gpr32 = COPY %3
+    BEQ undef %4:gpr32, $zero, %bb.2, implicit-def $at
 
- bb.3:
+  bb.3:
 
 ...
 
 # We should not hoist the
 #
-#  %22:gpr32 = COPY %21
+#  %1:gpr32 = COPY %0
 #
-# into bb.1 since %22 is used in the BEQ.
+# into bb.1 since %1 is used in the BEQ.
 
 # CHECK-LABEL: bb.1:
 # CHECK-NOT:      COPY
Index: llvm/lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1160,24 +1160,14 @@
   if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
     return false;
 
-  // Now (almost sure it's) ok to move copy.
+  // Now ok to move copy.
   if (CopyLeftBB) {
     // Position in CopyLeftBB where we should insert new copy.
     auto InsPos = CopyLeftBB->getFirstTerminator();
 
-    // Make sure that B isn't referenced in the terminators (if any) at the end
-    // of the predecessor since we're about to insert a new definition of B
-    // before them.
-    if (InsPos != CopyLeftBB->end()) {
-      SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
-      if (IntB.overlaps(InsPosIdx, LIS->getMBBEndIdx(CopyLeftBB)))
-        return false;
-    }
-
     LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
                       << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
 
-    // Insert new copy to CopyLeftBB.
     MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
                                       TII->get(TargetOpcode::COPY), IntB.reg())
                                   .addReg(IntA.reg());


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