[llvm] 0a5347f - [DAG] SimplifyDemandedBits - Use DemandedBits intead of OriginalDemandedBits to when simplifying UMIN/UMAX to AND/OR.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-08-18T11:59:18-07:00
New Revision: 0a5347f40d8a5298d8815076ce85bf5de58083b5

URL: https://github.com/llvm/llvm-project/commit/0a5347f40d8a5298d8815076ce85bf5de58083b5
DIFF: https://github.com/llvm/llvm-project/commit/0a5347f40d8a5298d8815076ce85bf5de58083b5.diff

LOG: [DAG] SimplifyDemandedBits - Use DemandedBits intead of OriginalDemandedBits to when simplifying UMIN/UMAX to AND/OR.

DemandedBits is forced to all ones if there are multiple users.

The changes X86 test cases looks like they were miscompiles before.
The value of eax/rax from the cmov is returned from the function in
addition to being used by the sar. That usage needs all bits even
though the sar doesn't.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/X86/umax.ll
    llvm/test/CodeGen/X86/umin.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 61b4377337afe2..4eb48e65df6084 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2139,7 +2139,7 @@ bool TargetLowering::SimplifyDemandedBits(
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
     // If we're only wanting the msb, then we can simplify to AND node.
-    if (OriginalDemandedBits.isSignMask())
+    if (DemandedBits.isSignMask())
       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));
     // Check if one arg is always less than (or equal) to the other arg.
     KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
@@ -2155,7 +2155,7 @@ bool TargetLowering::SimplifyDemandedBits(
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
     // If we're only wanting the msb, then we can simplify to OR node.
-    if (OriginalDemandedBits.isSignMask())
+    if (DemandedBits.isSignMask())
       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
     // Check if one arg is always greater than (or equal) to the other arg.
     KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);

diff  --git a/llvm/test/CodeGen/X86/umax.ll b/llvm/test/CodeGen/X86/umax.ll
index 4ebbcc4942e211..e6b39eb8b95229 100644
--- a/llvm/test/CodeGen/X86/umax.ll
+++ b/llvm/test/CodeGen/X86/umax.ll
@@ -1287,7 +1287,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    cmpl %eax, %ecx
+; X86-NEXT:    cmoval %ecx, %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -1302,7 +1304,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    orq %rsi, %rax
+; X64-NEXT:    cmpq %rax, %rsi
+; X64-NEXT:    cmovaq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq

diff  --git a/llvm/test/CodeGen/X86/umin.ll b/llvm/test/CodeGen/X86/umin.ll
index e5d743ed796f24..e1538aaaeba654 100644
--- a/llvm/test/CodeGen/X86/umin.ll
+++ b/llvm/test/CodeGen/X86/umin.ll
@@ -702,7 +702,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    cmpl %eax, %ecx
+; X86-NEXT:    cmovbl %ecx, %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -717,7 +719,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    andq %rsi, %rax
+; X64-NEXT:    cmpq %rax, %rsi
+; X64-NEXT:    cmovbq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq