[llvm] 29b2009 - Revert "[DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively."
Thurston Dang via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 18 11:08:45 PDT 2023
Author: Thurston Dang
Date: 2023-08-18T18:08:10Z
New Revision: 29b200906155da393b83232dd31d746ba2ad66a5
URL: https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5
DIFF: https://github.com/llvm/llvm-project/commit/29b200906155da393b83232dd31d746ba2ad66a5.diff
LOG: Revert "[DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively."
This reverts commit 54d663d5896008c09c938f80357e2a056454bc65, which breaks the test CodeGen/SystemZ/ctpop-01.ll for stage2-ubsan check (see https://lab.llvm.org/buildbot/#/builders/85/builds/18410)
I manually confirmed that the test had been passing immediately prior to that commit
(BUILDBOT_REVISION=4772c66cfb00d60f8f687930e9dd3aa1b6872228 llvm-zorg/zorg/buildbot/builders/sanitizers/buildbot_bootstrap_ubsan.sh)
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/X86/smax.ll
llvm/test/CodeGen/X86/smin.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 8bb6724593574c..61b4377337afe2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1688,22 +1688,6 @@ bool TargetLowering::SimplifyDemandedBits(
Known.Zero.setBitsFrom(1);
break;
}
- case ISD::SMIN: {
- SDValue Op0 = Op.getOperand(0);
- SDValue Op1 = Op.getOperand(1);
- // If we're only wanting the signbit, then we can simplify to OR node.
- if (OriginalDemandedBits.isSignMask())
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
- break;
- }
- case ISD::SMAX: {
- SDValue Op0 = Op.getOperand(0);
- SDValue Op1 = Op.getOperand(1);
- // If we're only wanting the signbit, then we can simplify to AND node.
- if (OriginalDemandedBits.isSignMask())
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));
- break;
- }
case ISD::SHL: {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
diff --git a/llvm/test/CodeGen/X86/smax.ll b/llvm/test/CodeGen/X86/smax.ll
index 55ee5d50619bd3..d6906b573981ac 100644
--- a/llvm/test/CodeGen/X86/smax.ll
+++ b/llvm/test/CodeGen/X86/smax.ll
@@ -692,7 +692,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
; X86-LABEL: test_signbits_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovgl %ecx, %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: sarl $31, %edx
; X86-NEXT: retl
@@ -707,7 +709,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: sarq $28, %rax
-; X64-NEXT: andq %rsi, %rax
+; X64-NEXT: cmpq %rax, %rsi
+; X64-NEXT: cmovgq %rsi, %rax
; X64-NEXT: movq %rax, %rdx
; X64-NEXT: sarq $63, %rdx
; X64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/smin.ll b/llvm/test/CodeGen/X86/smin.ll
index bb53ec1bceb262..2b059557cdfb50 100644
--- a/llvm/test/CodeGen/X86/smin.ll
+++ b/llvm/test/CodeGen/X86/smin.ll
@@ -693,7 +693,9 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
; X86-LABEL: test_signbits_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovll %ecx, %eax
; X86-NEXT: movl %eax, %edx
; X86-NEXT: sarl $31, %edx
; X86-NEXT: retl
@@ -708,7 +710,8 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
; X64: # %bb.0:
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: sarq $28, %rax
-; X64-NEXT: orq %rsi, %rax
+; X64-NEXT: cmpq %rax, %rsi
+; X64-NEXT: cmovlq %rsi, %rax
; X64-NEXT: movq %rax, %rdx
; X64-NEXT: sarq $63, %rdx
; X64-NEXT: retq
More information about the llvm-commits
mailing list