[PATCH] D158292: [DAGCombiner][RISCV][AArch64][PowerPC] Restrict foldAndOrOfSETCC from using SMIN/SMAX where and OR/AND would do.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: kmitropoulou, foad, arsenm, RKSimon, iabg-sc, greened, t.p.northover, nemanjai.
Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, steven.zhang, s.egerton, shchenz, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, kristof.beyls, arichardson.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: wangpc, eopXD, MaskRay, wdng.
Herald added a project: LLVM.

This removes some diffs created by D153502 <https://reviews.llvm.org/D153502>.

I'm assuming an AND/OR won't be worse than an SMIN/SMAX. For
RISC-V at least, AND/OR can be a shorter encoding than SMIN/SMAX.

It's weird that we have two different functions responsible for
folding logic of setccs, but I'm not ready to try to untangle that.

I'm unclear if the PowerPC chang is a regression or not. It looks
like it might use more registers, but I don't understand PowerPC
register so I'm not sure.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158292

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll
  llvm/test/CodeGen/PowerPC/setcc-logic.ll
  llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D158292.551553.patch
Type: text/x-patch
Size: 4685 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230818/9087b40f/attachment.bin>