[PATCH] D152205: [Aarch64][SVE]SVE2] Enable tbl, tbl2 for shuffle lowering for fixed vector types.

[Dinar Temirbulatov via Phabricator via llvm-commits]

dtemirbulatov marked an inline comment as not done.
dtemirbulatov added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:25745-25749
+    // Filling up the remaining positions of the mask with 255 because for one
+    // byte per element and maximum possible 2048-bits register size this is the
+    // last range value.
+    else if (IsUndefOrZero && Offset >= NumElts)
+      Offset = 255;
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dtemirbulatov wrote:
> sdesmalen wrote:
> > What should happen if the vector type is `<256 x i8>` and IsUndefOrZero is `false` ?
> I think
I think we allowing this lowering to only one operand supported with SVE1 TBL.


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  https://reviews.llvm.org/D152205/new/

https://reviews.llvm.org/D152205