[PATCH] D158195: [RISCV] Combine (vrot{l,r} vxi16, 8) -> vrev8

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 551495.
luke added a comment.

Fix extraneous test diffs caused by dodgy rebase (filecheck prefixes are actually fine: 
sorry for the noise)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158195/new/

https://reviews.llvm.org/D158195

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -202,13 +202,13 @@
 ; ZVBB_V-LABEL: shuffle_v8i8_as_i16:
 ; ZVBB_V:       # %bb.0:
 ; ZVBB_V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB_V-NEXT:    vror.vi v8, v8, 8
+; ZVBB_V-NEXT:    vrev8.v v8, v8
 ; ZVBB_V-NEXT:    ret
 ;
 ; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i16:
 ; ZVBB_ZVE32X:       # %bb.0:
 ; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e16, m2, ta, ma
-; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 8
+; ZVBB_ZVE32X-NEXT:    vrev8.v v8, v8
 ; ZVBB_ZVE32X-NEXT:    ret
   %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
   ret <8 x i8> %shuffle
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
@@ -180,7 +180,7 @@
 ; ZVBB-LABEL: reverse_v2i8:
 ; ZVBB:       # %bb.0:
 ; ZVBB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT:    vror.vi v8, v8, 8
+; ZVBB-NEXT:    vrev8.v v8, v8
 ; ZVBB-NEXT:    ret
   %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
   ret <2 x i8> %res
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13664,6 +13664,24 @@
     if (SDValue V = performCONCAT_VECTORSCombine(N, DAG, Subtarget, *this))
       return V;
     break;
+  case RISCVISD::ROTR_VL:
+  case RISCVISD::ROTL_VL: {
+    // An i16 bitrotate of 8 in either direction is equivalent to a swapping the
+    // bytes (bswap). This is normally caught by a generic ISD::ROT{L,R}
+    // combine, but on fixed vectors they are legalized before they can be
+    // combined, so handle it later here too.
+    EVT VT = N->getValueType(0);
+    if (VT.getScalarType() == MVT::i16 &&
+        // The splat of 8 will have been legalized to a vmv_v_x_vl.
+        N->getOperand(1).getOpcode() == RISCVISD::VMV_V_X_VL &&
+        N->getOperand(1).getOperand(0).isUndef() &&
+        isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+        N->getOperand(1).getConstantOperandVal(1) == 8) {
+      return DAG.getNode(RISCVISD::BSWAP_VL, SDLoc(N), VT, N->getOperand(0),
+                         N->getOperand(2), N->getOperand(3), N->getOperand(4));
+    }
+    break;
+  }
   case RISCVISD::VMV_V_X_VL: {
     // Tail agnostic VMV.V.X only demands the vector element bitwidth from the
     // scalar input.


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