[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 551493.
luke added a comment.

Fix extra multiplication on x86, and fix test diffs that didn't get included


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157417/new/

https://reviews.llvm.org/D157417

Files:
  llvm/include/llvm/IR/Instructions.h
  llvm/lib/IR/Instructions.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

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