[llvm] 54d663d - [DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-08-18T11:35:34+01:00
New Revision: 54d663d5896008c09c938f80357e2a056454bc65

URL: https://github.com/llvm/llvm-project/commit/54d663d5896008c09c938f80357e2a056454bc65
DIFF: https://github.com/llvm/llvm-project/commit/54d663d5896008c09c938f80357e2a056454bc65.diff

LOG: [DAG] SimplifyDemandedBits - if we're only demanding the signbit, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

Alive2: https://alive2.llvm.org/ce/z/MehvFB

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/X86/smax.ll
    llvm/test/CodeGen/X86/smin.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 033d1a5c3954de..002ef1f2edf6f3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1688,6 +1688,22 @@ bool TargetLowering::SimplifyDemandedBits(
       Known.Zero.setBitsFrom(1);
     break;
   }
+  case ISD::SMIN: {
+    SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the signbit, then we can simplify to OR node.
+    if (OriginalDemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
+    break;
+  }
+  case ISD::SMAX: {
+    SDValue Op0 = Op.getOperand(0);
+    SDValue Op1 = Op.getOperand(1);
+    // If we're only wanting the signbit, then we can simplify to AND node.
+    if (OriginalDemandedBits.isSignMask())
+      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, Op1));
+    break;
+  }
   case ISD::SHL: {
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);

diff  --git a/llvm/test/CodeGen/X86/smax.ll b/llvm/test/CodeGen/X86/smax.ll
index d6906b573981ac..55ee5d50619bd3 100644
--- a/llvm/test/CodeGen/X86/smax.ll
+++ b/llvm/test/CodeGen/X86/smax.ll
@@ -692,9 +692,7 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    cmpl %eax, %ecx
-; X86-NEXT:    cmovgl %ecx, %eax
+; X86-NEXT:    andl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -709,8 +707,7 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    cmpq %rax, %rsi
-; X64-NEXT:    cmovgq %rsi, %rax
+; X64-NEXT:    andq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq

diff  --git a/llvm/test/CodeGen/X86/smin.ll b/llvm/test/CodeGen/X86/smin.ll
index 2b059557cdfb50..bb53ec1bceb262 100644
--- a/llvm/test/CodeGen/X86/smin.ll
+++ b/llvm/test/CodeGen/X86/smin.ll
@@ -693,9 +693,7 @@ define i64 @test_signbits_i64(i64 %a, i64 %b) nounwind {
 ; X86-LABEL: test_signbits_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    cmpl %eax, %ecx
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    sarl $31, %edx
 ; X86-NEXT:    retl
@@ -710,8 +708,7 @@ define i128 @test_signbits_i128(i128 %a, i128 %b) nounwind {
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    sarq $28, %rax
-; X64-NEXT:    cmpq %rax, %rsi
-; X64-NEXT:    cmovlq %rsi, %rax
+; X64-NEXT:    orq %rsi, %rax
 ; X64-NEXT:    movq %rax, %rdx
 ; X64-NEXT:    sarq $63, %rdx
 ; X64-NEXT:    retq