[PATCH] D158053: [Legalizer] Expand fmaximum and fminimum

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf updated this revision to Diff 551451.
qiucf retitled this revision from "[PowerPC] Implement llvm.maximum/minimum intrinsic" to "[Legalizer] Expand fmaximum and fminimum".
qiucf edited the summary of this revision.
qiucf added a comment.
Herald added subscribers: wangpc, luke, sunshaoce, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.

Move to generic expansion.

Some targets do not set legal status of fmaximum and fminimum properly, so after expansion added, legalizer goes into the expansion path. RISCV looks suspicious so I marked them as legal, but uncertain for ARM.

Also this call needs to be added into `VectorLegalizer::Expand`, which will make large case change, I think that's also because of the wrong action setting of fminimum/fmaximum.

PowerPC codegen is not optimal on VSX targets, further patch will be provided to optimize it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158053/new/

https://reviews.llvm.org/D158053

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
  llvm/test/CodeGen/ARM/fminmax-folds.ll
  llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
  llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll

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