[PATCH] D158253: [VE] Change the way of lowering store

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added a reviewer: efocht.
kaz7 added a project: VE.
Herald added a subscriber: hiraditya.
Herald added a project: All.
kaz7 requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Change lowering store iff the data operand is leagalized.  In this way,
llvm can lower only operands first, then lower store instruction later.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158253

Files:
  llvm/lib/Target/VE/VVPISelLowering.cpp
  llvm/test/CodeGen/VE/Vector/ticket-64420.ll


Index: llvm/test/CodeGen/VE/Vector/ticket-64420.ll
===================================================================
--- llvm/test/CodeGen/VE/Vector/ticket-64420.ll
+++ llvm/test/CodeGen/VE/Vector/ticket-64420.ll
@@ -1,11 +1,23 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
 ; RUN: llc < %s -mtriple=ve -mattr=-vpu | FileCheck --check-prefix=SCALAR %s
 
 ; Check vector and scalar code generation for vector load instruction.
-; For the case of scalar, generates 2 stores of 8 bytes length.
+; For the case of vector, generates vst with 4 vector length.  For the
+; case of scalar, generates 2 stores of 8 bytes length.
 
 ; This is taken from a ticket below.
 ;   https://github.com/llvm/llvm-project/issues/64420
 
+; CHECK-LABEL: func:
+; CHECK:       # %bb.1:
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    vbrd %v0, 0
+; CHECK-NEXT:    or %s1, 4, (0)1
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    vstl %v0, 4, %s0
+; CHECK-NEXT:    b.l.t (, %s10)
+
 ; SCALAR-LABEL: func:
 ; SCALAR:       # %bb.1:
 ; SCALAR-NEXT:    st %s1, 8(, %s0)
Index: llvm/lib/Target/VE/VVPISelLowering.cpp
===================================================================
--- llvm/lib/Target/VE/VVPISelLowering.cpp
+++ llvm/lib/Target/VE/VVPISelLowering.cpp
@@ -169,6 +169,12 @@
 
   // VVP_STORE
   assert(VVPOpc == VEISD::VVP_STORE);
+  if (getTypeAction(*CDAG.getDAG()->getContext(), Data.getValueType()) !=
+      TargetLowering::TypeLegal)
+    // Doesn't lower store instruction if an operand is not lowered yet.
+    // If it isn't, return SDValue().  In this way, LLVM will try to lower
+    // store instruction again after lowering all operands.
+    return SDValue();
   return CDAG.getNode(VEISD::VVP_STORE, Op.getNode()->getVTList(),
                       {Chain, Data, BasePtr, StrideV, Mask, AVL});
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D158253.551409.patch
Type: text/x-patch
Size: 1841 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230818/ce813f87/attachment.bin>