[PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion

[Kito Cheng via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0816b3efbfaa: [RISCV] Check floating point vector instruction with SEW=64 is valid when… (authored by kito-cheng).

Changed prior to commit:
  https://reviews.llvm.org/D158086?vs=551100&id=551355#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158086/new/

https://reviews.llvm.org/D158086

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll


Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
@@ -9,6 +9,7 @@
 ; CHECK-NO-FELEN64:       # %bb.0: # %entry
 ; CHECK-NO-FELEN64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-NO-FELEN64-NEXT:    vle64.v v8, (a0)
+; CHECK-NO-FELEN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
 ; CHECK-NO-FELEN64-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NO-FELEN64-NEXT:    #APP
 ; CHECK-NO-FELEN64-NEXT:    # use v8 v9
@@ -39,6 +40,7 @@
 ; CHECK-NO-FELEN64:       # %bb.0: # %entry
 ; CHECK-NO-FELEN64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
 ; CHECK-NO-FELEN64-NEXT:    vle32.v v8, (a0)
+; CHECK-NO-FELEN64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
 ; CHECK-NO-FELEN64-NEXT:    vfmv.s.f v9, fa0
 ; CHECK-NO-FELEN64-NEXT:    #APP
 ; CHECK-NO-FELEN64-NEXT:    # use v8 v9
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -75,6 +75,16 @@
   return RVV->BaseInstr;
 }
 
+static bool isFloatScalarMoveOrScalarSplatInstr(const MachineInstr &MI) {
+  switch (getRVVMCOpcode(MI.getOpcode())) {
+  default:
+    return false;
+  case RISCV::VFMV_S_F:
+  case RISCV::VFMV_V_F:
+    return true;
+  }
+}
+
 static bool isScalarExtractInstr(const MachineInstr &MI) {
   switch (getRVVMCOpcode(MI.getOpcode())) {
   default:
@@ -321,6 +331,8 @@
   // emitVSETVLIs) and pre-lowering forms.  The main implication of this is
   // that it can't use the value of a SEW, VL, or Policy operand as they might
   // be stale after lowering.
+  bool HasVInstructionsF64 =
+      MI.getMF()->getSubtarget<RISCVSubtarget>().hasVInstructionsF64();
 
   // Most instructions don't use any of these subfeilds.
   DemandedFields Res;
@@ -379,7 +391,8 @@
     // tail lanes to either be the original value or -1.  We are writing
     // unknown bits to the lanes here.
     if (hasUndefinedMergeOp(MI, *MRI)) {
-      Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
+      if (!isFloatScalarMoveOrScalarSplatInstr(MI) || HasVInstructionsF64)
+        Res.SEW = DemandedFields::SEWGreaterThanOrEqual;
       Res.TailPolicy = false;
     }
   }
@@ -935,6 +948,8 @@
     return true;
 
   DemandedFields Used = getDemanded(MI, MRI);
+  bool HasVInstructionsF64 =
+      MI.getMF()->getSubtarget<RISCVSubtarget>().hasVInstructionsF64();
 
   // A slidedown/slideup with an *undefined* merge op can freely clobber
   // elements not copied from the source vector (e.g. masked off, tail, or
@@ -962,7 +977,8 @@
     Used.LMUL = false;
     Used.SEWLMULRatio = false;
     Used.VLAny = false;
-    Used.SEW = DemandedFields::SEWGreaterThanOrEqual;
+    if (!isFloatScalarMoveOrScalarSplatInstr(MI) || HasVInstructionsF64)
+      Used.SEW = DemandedFields::SEWGreaterThanOrEqual;
     Used.TailPolicy = false;
   }
 


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