[PATCH] D158161: [RISCV] Don't relax policy to ta when vmerge's VL shrinks during folding

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3512
+  bool MergeVLShrunk = VL != OrigVL;
+  uint64_t Policy = (isImplicitDef(Merge) && !MergeVLShrunk) ? RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
   SDValue PolicyOp =
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reames wrote:
> If instead, we were to change this line to:
> ```
> uint64_t Policy = isImplicitDef(False)  ? RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
> 
> ```
> What would happen?  I'm worried there's some other case we haven't caught where Merge was implicit_def, but the resulting operation has a non-implicit_def result.  I think *all* such cases needs to be TU.  
Answer: A lot of regressions.  I tried this, and it definitely doesn't seem to work.

I'm still a bit worried there's another case here.  I don't have anything specific though.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158161/new/

https://reviews.llvm.org/D158161