[PATCH] D158195: [RISCV] Combine (vrot{l,r} vxi16, 8) -> vrev8

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 17 10:29:49 PDT 2023


craig.topper added a comment.

If the rotate came in as a fshl/fshr intrinsic or as shl+shr+or would we already get vrev8 for fixed vectors? Is only the shuffle case that is being optimized?



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll:278
+; ZVBB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
+; ZVBB-NEXT:    vror.vi v8, v8, 16
+; ZVBB-NEXT:    ret
----------------
How does this patch create new rotates?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158195/new/

https://reviews.llvm.org/D158195



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