[PATCH] D156831: [AArch64][GlobalISel] Legalize integer across-lane intrinsics with actual type

[Vladislav Dzhidzhoev via Phabricator via llvm-commits]

dzhidzhoev updated this revision to Diff 551149.
dzhidzhoev added a comment.

Addressed @dmgreen comments.
Changed references of bf16 to f16.
Removed changes modifying RegBankSelect behaviour related to G_ZEXT. Used GIIgnoreCopies flag in patterns to select sext/zext(uaddv/saddv/...) used by 
laneop.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156831/new/

https://reviews.llvm.org/D156831

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrGISel.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/arm64-smaxv.ll
  llvm/test/CodeGen/AArch64/arm64-sminv.ll
  llvm/test/CodeGen/AArch64/arm64-umaxv.ll
  llvm/test/CodeGen/AArch64/arm64-uminv.ll
  llvm/test/CodeGen/AArch64/arm64-vaddv.ll

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