[PATCH] D156101: [AMDGPU] Introduce real and keep fake True16 instructions.

Ivan Kosarev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 17 06:46:42 PDT 2023


kosarev marked an inline comment as done.
kosarev added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h:147-157
+  template <typename InsnType>
+  DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
+                             MCInst &MI, InsnType Inst, uint64_t Address,
+                             raw_ostream &Comments) const {
+    for (const uint8_t *T : {Table1, Table2}) {
+      if (DecodeStatus Res = tryDecodeInst(T, MI, Inst, Address, Comments))
+        return Res;
----------------
arsenm wrote:
> Can just submit this cleanup on its own
Not a clean-up (though it can be). We use that for the FAKE16 tables, which don't exist prior this patch.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2694
   (fcanonicalize (f16 (fneg (VOP3Mods f16:$src, i32:$src_mods)))),
-  (V_MUL_F16_t16_e64 0, (i32 CONST.FP16_NEG_ONE), $src_mods, $src)
 >;
----------------
arsenm wrote:
> I'm assuming the end goal is to bring back a more sensible naming?
Yes, fake16 entities are not supposed to stay. At some point a t16 variant of the pattern should be added and then the support for fake instructions should be removed after switching to using real True16 instructions by default.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156101/new/

https://reviews.llvm.org/D156101



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