[PATCH] D152828: [MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode

[Momchil Velikov via Phabricator via llvm-commits]

chill added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:3264
+      unsigned Opcode = regOffsetOpcode(MemI.getOpcode());
+      // Copy the base register to the correct register class.
+      Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
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chill wrote:
> chill wrote:
> > dmgreen wrote:
> > > Would constrainRegClass work too, to avoid the COPY?
> > We come here with virtual register in `AM.BaseReg` in the `GPR64` register class, but the load/store instruction needs a register in the `GPR64sp`, which is not a subclass of `GPR64` (it's less constrained, a superclass).
> > 
> > IIUC, `constrainRegClass` would work in the opposite direction of what we need, from `GPR64sp` to `GPR64`.
> > 
> > Alternatively, that might be fixed in the verifier, to not complain if an operand is not in the exact register class, but is nevertheless in a more constrained class (a subclass).
> All right, having said that, I just tried using `constrainRegClass`  and it worked.  I'll look some more into it.
I see what happens, neither one of `GPR64` or `GPR64sp` is a superclass/subclass of the other as I thought (one has `XZR`  where the other has `SP`). So `constrainRegClass` yields `GPR64common` and the machine verifier already works exactly suggested above.


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  https://reviews.llvm.org/D152828/new/

https://reviews.llvm.org/D152828