[PATCH] D158138: [RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp.

Wed Aug 16 19:51:51 PDT 2023

jrtc27 added a comment.

In D158138#4593982 <https://reviews.llvm.org/D158138#4593982>, @craig.topper wrote:

> In D158138#4593976 <https://reviews.llvm.org/D158138#4593976>, @jrtc27 wrote:
>
>> In D158138#4593975 <https://reviews.llvm.org/D158138#4593975>, @craig.topper wrote:
>>
>>> In D158138#4593972 <https://reviews.llvm.org/D158138#4593972>, @jrtc27 wrote:
>>>
>>>> https://github.com/riscv/riscv-cfi/issues/125#issuecomment-1681520704
>>>
>>> Is it because x7 is the landing pad label? So if the call used x7 as the address then its clearly does not contain a landing pad label? I'm just guessing.
>>
>> So why not make x6 the landing pad label if they want everything to be in one register...
>
> Software guarded branches changed to x6 here https://github.com/riscv/riscv-cfi/commit/aaea3077bc4256dd56b07403cd1b88ca46b83c27 but then changed back https://github.com/riscv/riscv-cfi/commit/afbc2d5544f8ceda4a69d4c1ba17efc7c2c639d3

I found as much, but not any justification for these changes anywhere, just unhelpful commits that don't document any rationale.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158138/new/

https://reviews.llvm.org/D158138