[PATCH] D155071: [RISCV] Fold vmerge into its ops with smaller VL if known

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Here's a hack to avoid the buggy case

  diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  index dfa54740c0d6..ad3f0e98d12f 100644
  --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  @@ -3629,7 +3629,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
     SDValue TrueVL = True.getOperand(TrueVLIndex);
     SDValue SEW = True.getOperand(TrueVLIndex + 1);
   
  -  auto GetMinVL = [](SDValue LHS, SDValue RHS) {
  +  auto GetMinVL = [&](SDValue LHS, SDValue RHS) {
       if (LHS == RHS)
         return LHS;
       if (isAllOnesConstant(LHS))
  @@ -3640,7 +3640,11 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
       auto *CRHS = dyn_cast<ConstantSDNode>(RHS);
       if (!CLHS || !CRHS)
         return SDValue();
  -    return CLHS->getZExtValue() <= CRHS->getZExtValue() ? LHS : RHS;
  +    if (CRHS->getZExtValue() <= CLHS->getZExtValue())
  +      return RHS;
  +    if (isImplicitDef(Merge))
  +      return SDValue();
  +    return LHS;
     };
   
     // Because N and True must have the same merge operand (or True's operand is


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https://reviews.llvm.org/D155071