[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 16 16:22:57 PDT 2023
craig.topper added a comment.
I think I'm seeing a miscompile from this
I have a tail undefined unmasked vrgather.vi with VL=2 followed by a tail undefined vmerge with VL=4. This gets combined to a tail agnostic masked undisturbed masked vrgather.vi with VL =2. I think this needs to be a tail undisturbed VL to account for elements 2 and 3 from the vmerge becoming part of the tail?
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https://reviews.llvm.org/D155288/new/
https://reviews.llvm.org/D155288
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