[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 550876.
craig.topper added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155288/new/

https://reviews.llvm.org/D155288

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/CodeGen/RISCV/condops.ll
  llvm/test/CodeGen/RISCV/double-select-icmp.ll
  llvm/test/CodeGen/RISCV/float-select-icmp.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/half-select-icmp.ll
  llvm/test/CodeGen/RISCV/select-cc.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155288.550876.patch
Type: text/x-patch
Size: 121323 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230816/ecde45cb/attachment-0001.bin>