[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

I happened to see a case which looked a lot like this on RV64 where the user was a branch (probably not a lowered select, but not 100% sure).  Could we extend this to a SETCC feeding a BRCOND as well?  Doing this during DAG (vs only lowering) might expose more CSE opportunities.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12609
+  if (CondVal.getOpcode() == ISD::SETCC &&
+      setCCWillBeInvertedWhenLegalized(CondVal)) {
+    SDLoc DL(N);
----------------
This seems to have a decent amount of overlap with translateSetCCForBranch which we do during lowering of both branch and select.  Could we maybe reuse that set of transforms here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155288/new/

https://reviews.llvm.org/D155288