[llvm] 42dad52 - [RISCV] Add RISCVII::getRoundModeOpNum to reduce code duplication. NFC

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 16 12:03:05 PDT 2023


Author: Craig Topper
Date: 2023-08-16T12:00:02-07:00
New Revision: 42dad521e33e019d465cb81b74abe49b8d3832fc

URL: https://github.com/llvm/llvm-project/commit/42dad521e33e019d465cb81b74abe49b8d3832fc
DIFF: https://github.com/llvm/llvm-project/commit/42dad521e33e019d465cb81b74abe49b8d3832fc.diff

LOG: [RISCV] Add RISCVII::getRoundModeOpNum to reduce code duplication. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index f86419319dd3a4..33fc01208d8523 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -175,6 +175,20 @@ static inline bool hasRoundModeOp(uint64_t TSFlags) {
   return TSFlags & HasRoundModeOpMask;
 }
 
+/// \returns  the index to the rounding mode immediate value if any, otherwise
+/// returns -1.
+static inline int getRoundModeOpNum(const MCInstrDesc &Desc) {
+  const uint64_t TSFlags = Desc.TSFlags;
+  if (!hasRoundModeOp(TSFlags))
+    return -1;
+  // The operand order
+  // -------------------------------------
+  // | n-1 (if any)   | n-2  | n-3 | n-4 |
+  // | policy         | sew  | vl  | rm  |
+  // -------------------------------------
+  return Desc.getNumOperands() - hasVecPolicyOp(TSFlags) - 3;
+}
+
 /// \returns true if this instruction uses vxrm
 static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
 

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 24351a14eefe09..0e1e578ad2c0cb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14922,27 +14922,13 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   }
 }
 
-// Returns the index to the rounding mode immediate value if any, otherwise the
-// function will return None.
-static std::optional<unsigned> getRoundModeIdx(const MachineInstr &MI) {
-  uint64_t TSFlags = MI.getDesc().TSFlags;
-  if (!RISCVII::hasRoundModeOp(TSFlags))
-    return std::nullopt;
-
-  // The operand order
-  // -------------------------------------
-  // | n-1 (if any)   | n-2  | n-3 | n-4 |
-  // | policy         | sew  | vl  | rm  |
-  // -------------------------------------
-  return MI.getNumExplicitOperands() - RISCVII::hasVecPolicyOp(TSFlags) - 3;
-}
-
 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
                                                         SDNode *Node) const {
   // Add FRM dependency to vector floating-point instructions with dynamic
   // rounding mode.
-  if (auto RoundModeIdx = getRoundModeIdx(MI)) {
-    unsigned FRMImm = MI.getOperand(*RoundModeIdx).getImm();
+  int RoundModeIdx = RISCVII::getRoundModeOpNum(MI.getDesc());
+  if (RoundModeIdx >=  0) {
+    unsigned FRMImm = MI.getOperand(RoundModeIdx).getImm();
     if (FRMImm == RISCVFPRndMode::DYN && !MI.readsRegister(RISCV::FRM)) {
       MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false,
                                               /*isImp*/ true));

diff  --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
index 4b26c27bb4f8ef..cb08c6b4178561 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
@@ -56,59 +56,46 @@ char RISCVInsertReadWriteCSR::ID = 0;
 INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
                 RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
 
-// Returns the index to the rounding mode immediate value if any, otherwise the
-// function will return None.
-static std::optional<unsigned> getRoundModeIdx(const MachineInstr &MI) {
-  uint64_t TSFlags = MI.getDesc().TSFlags;
-  if (!RISCVII::hasRoundModeOp(TSFlags))
-    return std::nullopt;
-
-  // The operand order
-  // -------------------------------------
-  // | n-1 (if any)   | n-2  | n-3 | n-4 |
-  // | policy         | sew  | vl  | rm  |
-  // -------------------------------------
-  return MI.getNumExplicitOperands() - RISCVII::hasVecPolicyOp(TSFlags) - 3;
-}
-
 // This function inserts a write to vxrm when encountering an RVV fixed-point
 // instruction.
 bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
   bool Changed = false;
   for (MachineInstr &MI : MBB) {
-    if (auto RoundModeIdx = getRoundModeIdx(MI)) {
-      if (RISCVII::usesVXRM(MI.getDesc().TSFlags)) {
-        unsigned VXRMImm = MI.getOperand(*RoundModeIdx).getImm();
-
-        Changed = true;
-
-        BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
-            .addImm(VXRMImm);
-        MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
-                                                /*IsImp*/ true));
-      } else { // FRM
-        unsigned FRMImm = MI.getOperand(*RoundModeIdx).getImm();
-
-        // The value is a hint to this pass to not alter the frm value.
-        if (FRMImm == RISCVFPRndMode::DYN)
-          continue;
-
-        Changed = true;
-
-        // Save
-        MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
-        Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
-        BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
-                SavedFRM)
-            .addImm(FRMImm);
-        MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
-                                                /*IsImp*/ true));
-        // Restore
-        MachineInstrBuilder MIB =
-            BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
-                .addReg(SavedFRM);
-        MBB.insertAfter(MI, MIB);
-      }
+    int RoundModeIdx = RISCVII::getRoundModeOpNum(MI.getDesc());
+    if (RoundModeIdx < 0)
+      continue;
+
+    if (RISCVII::usesVXRM(MI.getDesc().TSFlags)) {
+      unsigned VXRMImm = MI.getOperand(RoundModeIdx).getImm();
+
+      Changed = true;
+
+      BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
+          .addImm(VXRMImm);
+      MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
+                                              /*IsImp*/ true));
+    } else { // FRM
+      unsigned FRMImm = MI.getOperand(RoundModeIdx).getImm();
+
+      // The value is a hint to this pass to not alter the frm value.
+      if (FRMImm == RISCVFPRndMode::DYN)
+        continue;
+
+      Changed = true;
+
+      // Save
+      MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
+      Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+      BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
+              SavedFRM)
+          .addImm(FRMImm);
+      MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
+                                              /*IsImp*/ true));
+      // Restore
+      MachineInstrBuilder MIB =
+          BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
+              .addReg(SavedFRM);
+      MBB.insertAfter(MI, MIB);
     }
   }
   return Changed;


        


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