[PATCH] D158049: [VE] Avoid vectorizing store/load in scalar mode

[Kazushi Marukawa via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG922ac64b04b1: [VE] Avoid vectorizing store/load in scalar mode (authored by kaz7).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158049/new/

https://reviews.llvm.org/D158049

Files:
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/test/CodeGen/VE/Vector/ticket-64420.ll


Index: llvm/test/CodeGen/VE/Vector/ticket-64420.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/VE/Vector/ticket-64420.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=ve -mattr=-vpu | FileCheck --check-prefix=SCALAR %s
+
+; Check vector and scalar code generation for vector load instruction.
+; For the case of scalar, generates 2 stores of 8 bytes length.
+
+; This is taken from a ticket below.
+;   https://github.com/llvm/llvm-project/issues/64420
+
+; SCALAR-LABEL: func:
+; SCALAR:       # %bb.1:
+; SCALAR-NEXT:    st %s1, 8(, %s0)
+; SCALAR-NEXT:    st %s1, (, %s0)
+; SCALAR-NEXT:    b.l.t (, %s10)
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+source_filename = "test.c"
+target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64"
+target triple = "ve-unknown-linux-gnu"
+
+define dso_local void @func(ptr %_0) unnamed_addr #0 {
+start:
+  br i1 poison, label %bb7, label %panic3
+
+bb7:                                              ; preds = %start
+  store <4 x i32> zeroinitializer, ptr %_0, align 4
+  ret void
+
+panic3:                                           ; preds = %start
+  unreachable
+}
+
+attributes #0 = { "target-features"="+vpu" }
Index: llvm/lib/Target/VE/VEISelLowering.cpp
===================================================================
--- llvm/lib/Target/VE/VEISelLowering.cpp
+++ llvm/lib/Target/VE/VEISelLowering.cpp
@@ -1428,11 +1428,10 @@
 
 SDValue VETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
   LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
-
   EVT MemVT = LdNode->getMemoryVT();
 
-  // Dispatch to vector isel.
-  if (MemVT.isVector() && !isMaskType(MemVT))
+  // If VPU is enabled, always expand non-mask vector loads to VVP
+  if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(MemVT))
     return lowerToVVP(Op, DAG);
 
   SDValue BasePtr = LdNode->getBasePtr();
@@ -1542,10 +1541,10 @@
 SDValue VETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
   StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
   assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
-
-  // always expand non-mask vector loads to VVP
   EVT MemVT = StNode->getMemoryVT();
-  if (MemVT.isVector() && !isMaskType(MemVT))
+
+  // If VPU is enabled, always expand non-mask vector stores to VVP
+  if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(MemVT))
     return lowerToVVP(Op, DAG);
 
   SDValue BasePtr = StNode->getBasePtr();


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