[PATCH] D154805: [DAGCombiner] Fold IEEE `fmul`/`fdiv` by Pow2 to `add`/`sub` of exp

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:822-823
+                                                   SDValue IntPow2) const {
+    // Default to avoiding fdiv which is often very expensive.
+    return N->getOpcode() == ISD::FDIV;
+  }
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I think the fdiv by power of 2 should be generally converted to fmul by inverse power of 2 in the first place


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:16220
+      case ISD::ZERO_EXTEND:
+      case ISD::ANY_EXTEND:
+        V = V.getOperand(0);
----------------
ANY_EXTEND seems dangerous here


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154805/new/

https://reviews.llvm.org/D154805