[PATCH] D158015: [RISCVInsertVSETVLI] Default to VL=1 for scalar extracts

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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We were defaulting to VL=0 when we didn't otherwise have a vsetv nearby.  Instead, let's use VL=1.  VL=0 is very much a cornercase in hardware, and let's avoid if we can.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158015

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/test/CodeGen/RISCV/double_reduct.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

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